Browse Prior Art Database

Memory Protect Circuit During Power Interruption

IP.com Disclosure Number: IPCOM000047078D
Original Publication Date: 1983-Sep-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 27K

Publishing Venue

IBM

Related People

Ehrsam, WF: AUTHOR

Abstract

A memory protect circuit arrangement is disclosed for protecting the contents of a battery-powered, volatile memory during power transients on the signal lines when the system power is applied or removed. Secure cryptographic master key storage may be obtained by storing the key in a volatile memory, such as a CMOS random-access memory (RAM) device, which is selected because of its low stand-by power requirements. Accordingly, the device is powered with a battery such that the RAM retains its information as long as the battery is connected and loses its information when the circuit card containing the RAM is removed from its socket.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 70% of the total text.

Page 1 of 2

Memory Protect Circuit During Power Interruption

A memory protect circuit arrangement is disclosed for protecting the contents of a battery-powered, volatile memory during power transients on the signal lines when the system power is applied or removed. Secure cryptographic master key storage may be obtained by storing the key in a volatile memory, such as a CMOS random-access memory (RAM) device, which is selected because of its low stand-by power requirements. Accordingly, the device is powered with a battery such that the RAM retains its information as long as the battery is connected and loses its information when the circuit card containing the RAM is removed from its socket. A problem exists, however, when voltage is applied to or removed from the circuit modules driving the RAM signal lines causing transients (glitches) to occur on the signal lines which, if uncontrolled on the Not- Memory Enable (-ME) line, causes unpredictable changes in the information contained in the RAM even though the battery voltage and the Not-Write Enable (-WE) signal line of the RAM are held constant via the battery at a high level. The circuit disclosed here eliminates the glitches from reaching the RAM by monitoring the power supply voltage with a Zener diode circuit, as shown in the figure. The memory enable interrupt circuit consists of a transistor (TR) used to open up the -ME line and a Zener diode (ZD) used to sense a low voltage condition of the power supply (VS). The ba...