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Self-Clocking Nrz Digital Communications

IP.com Disclosure Number: IPCOM000047081D
Original Publication Date: 1983-Sep-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 32K

Publishing Venue

IBM

Related People

Ellis, JJ: AUTHOR

Abstract

The ability to extract the data clock from the communication protocol used in conjunction with a fiber-optic data link would significantly reduce the cost of transmitting data over long distances. This article describes a self-clocking NRX protocol which is an adaptation of the Start/Stop protocol with parity where the message length is a predefined. During the interval between messages, the transmitter output will change state at the end of each bit time and will remain in phase with the reference idle line, as illustrated in Fig. 1. The Start Bit 1 for the message is identified by the absence of a transition between bit times. The data bits within the message are encoded using the lack of a transition to indicate either a logical zero or a one.

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Self-Clocking Nrz Digital Communications

The ability to extract the data clock from the communication protocol used in conjunction with a fiber-optic data link would significantly reduce the cost of transmitting data over long distances. This article describes a self-clocking NRX protocol which is an adaptation of the Start/Stop protocol with parity where the message length is a predefined. During the interval between messages, the transmitter output will change state at the end of each bit time and will remain in phase with the reference idle line, as illustrated in Fig. 1. The Start Bit 1 for the message is identified by the absence of a transition between bit times. The data bits within the message are encoded using the lack of a transition to indicate either a logical zero or a one. A Phase Correction Bit 2, which is analogous to parity, is inserted at the end of the message to restore synchronization with the phase of the reference idle line. A block diagram for the receiver is shown in Fig.
2. The receiver consists of a phase-locked loop (PLL) which is synchronized to the idle line. By operating the PLL at twice the frequency of the idle line, the PLL output can be used as the Data Clock 4. The PLL will drift during the message due to the random nature of the data transitions. The drift can be minimized by generating a signal 5 which is equivalent to the reference idle line used by the transmitter. During the idle condition between messages, switch 6 gates...