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Browse Prior Art Database

Selectable Circuit Master Slice

IP.com Disclosure Number: IPCOM000047085D
Original Publication Date: 1983-Sep-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 3 page(s) / 48K

Publishing Venue

IBM

Related People

Hoover, RA: AUTHOR

Abstract

Fig. 1 illustrates a three-input NOR with a 3X current capability employing the selectable circuit master slice invention, and Fig. 2 is the circuit schematic diagram for the NOR circuit. The chip image for the selectable circuit master slice comprises horizontal regions, each such region consisting of two parts: a lower portion consisting of the spaced, mutually parallel rows of horizontal diffusion segments Dij (employing the matrix notation shown in Fig. 1) which serve to form the active FET logic devices, and an upper portion consisting of the spaced pairs of diffusions Ldj (drain diffusions) and Lsj (source diffusions) which will form self-biased load devices which are juxtaposed with the corresponding active FET devices in the lower portion. The three-input NOR circuit with a 3X current drive capability of Fig.

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Selectable Circuit Master Slice

Fig. 1 illustrates a three-input NOR with a 3X current capability employing the selectable circuit master slice invention, and Fig. 2 is the circuit schematic diagram for the NOR circuit. The chip image for the selectable circuit master slice comprises horizontal regions, each such region consisting of two parts: a lower portion consisting of the spaced, mutually parallel rows of horizontal diffusion segments Dij (employing the matrix notation shown in Fig. 1) which serve to form the active FET logic devices, and an upper portion consisting of the spaced pairs of diffusions Ldj (drain diffusions) and Lsj (source diffusions) which will form self- biased load devices which are juxtaposed with the corresponding active FET devices in the lower portion. The three-input NOR circuit with a 3X current drive capability of Fig. 1 is comprised of devices A, B and C as the enhancement- mode active FET devices and the device L as the depletion-mode FET load device. Since a 3X current drive capability is desired for this circuit, the device A has its drain made up of three drain diffusions D12, D22 and D32 which are selectively contacted by the metal line 2 by means of via connections and are electrically connected to the polycrystalline silicon gate Lg1 . It is the metal level interconnection line 2, etc., which will serve to selectively program the desired circuit for the selectable circuit master slice layout. The source for the device A comprises the three diffusions D11, D21 and D31 which are connected in common by means of the programmable metal line 4 to the ground line GND. In a similar manner, the device B has its drain comprising the commonly connected diffusions D12, D22 and D32 and has as its source the three diffusions D13, D23 and D33 which are commonly connected by means of the programmable metal line 6 to the ground line GND. In a similar manner, the device C has as its source the three diffusions D13, D23 and D33 and as its drain the three diffusions D14, D24 and D34 which are commonly connected by means of the programmable metal line 8 to the horizontal metal line 10. The horizontal metal line 10 joins vertical line 2 with vertical line 8 and connects them by means of via connections to the three load device gates Lg1, Lg2 and Lg3 . The load L is desired to be a 3X current capacity device, and therefore three component load device elements a...