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FET Voltage Regulator Circuit

IP.com Disclosure Number: IPCOM000047087D
Original Publication Date: 1983-Sep-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 22K

Publishing Venue

IBM

Related People

Burke, RD: AUTHOR

Abstract

An FET regulator circuit is disclosed which maintains a relatively constant bias voltage over a given temperature range. Transistors 2 and 1 form a voltage divider. The output voltage at node A is the same as the threshold voltage of transistor 1. Node A is fed to the gate of transistor 3 which forms an output voltage on node BIAS which is two threshold voltages above ground potential. This output voltage is compensated in temperature by the threshold shifts with temperatures of transistors 1 and 3 which sum out algebraically to form a zero dependence on temperature. Transistor 1 is an enhancement-mode device and transistors 2 and 3 are depletion-mode devices. The temperature rise causes the threshold of transistor 1 to decrease, causing node A to decrease.

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FET Voltage Regulator Circuit

An FET regulator circuit is disclosed which maintains a relatively constant bias voltage over a given temperature range. Transistors 2 and 1 form a voltage divider. The output voltage at node A is the same as the threshold voltage of transistor 1. Node A is fed to the gate of transistor 3 which forms an output voltage on node BIAS which is two threshold voltages above ground potential. This output voltage is compensated in temperature by the threshold shifts with temperatures of transistors 1 and 3 which sum out algebraically to form a zero dependence on temperature. Transistor 1 is an enhancement-mode device and transistors 2 and 3 are depletion-mode devices. The temperature rise causes the threshold of transistor 1 to decrease, causing node A to decrease. The same temperature rise causes the threshold voltage of transistor 3 to decrease. In that effect node A goes down but the threshold voltage of transistor 3 goes down, keeping node BIAS at the same potential.

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