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High Speed Testable Clock Pulse Generator Circuit

IP.com Disclosure Number: IPCOM000047094D
Original Publication Date: 1983-Sep-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 3 page(s) / 45K

Publishing Venue

IBM

Related People

Greenberg, R: AUTHOR

Abstract

This circuit provides output pulses from each of pre-drive blocks E1 to EN and F1 to FN at half the frequency of input oscillator O driving latch L, with each of the blocks of the circuit beyond the latch having no more than two inputs each to provide a high speed circuit and with -SCAN C and -SCAN B inputs utilizing parts of the circuit for testing purposes. Latch L is a latch of the "D" type well known in the art and has the D and CLK input terminals respectively for data and controlling clock pulses. Latch L also has output terminals Q and Q. Oscillator O is connected with the CLK terminal of latch L.

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High Speed Testable Clock Pulse Generator Circuit

This circuit provides output pulses from each of pre-drive blocks E1 to EN and F1 to FN at half the frequency of input oscillator O driving latch L, with each of the blocks of the circuit beyond the latch having no more than two inputs each to provide a high speed circuit and with -SCAN C and -SCAN B inputs utilizing parts of the circuit for testing purposes. Latch L is a latch of the "D" type well known in the art and has the D and CLK input terminals respectively for data and controlling clock pulses. Latch L also has output terminals Q and Q. Oscillator O is connected with the CLK terminal of latch L. When a "1" signal is applied to the D input of latch L and on the rise of a clock pulse from oscillator O, latch L will transfer the "1" from the D terminal to the Q terminal, and the latch will remain in this condition until the arrival of another clock pulse from the oscillator O. At that time, whatever signal is on the D input of latch L will be transferred to the Q terminal of this latch. For every time that the terminal Q rises to a "1" value, the value at the Q terminal of latch L is zero, and this terminal is connected with the D terminal of latch L, as shown, to impress zero signal on the D terminal of latch
L. Thus, the values on the Q and Q terminals alternate, each time in accordance with the impression of a clock pulse from oscillator O on latch L, so that the frequency of the output on the terminal Q or on the terminal Q is one-half the frequency of the oscillator O. Each of the blocks AA to AG in effect constitutes an inverter, providing a zero output when there is a "1" input. Block AA also constitutes an AND circuit and has the -SCAN C input. The blocks AA to AG are odd in number and thus, in effect, constitute a single inverter in final result but provide a delay which is desired. Under the condition in which the signal on the Q terminal is zero, while the signal on the Q terminal is "1", the zero signal from the terminal Q applied to the block AA causes a "1" signal to be applied from inverter AG to AND circuit CF. The terminal Q at this time, as just described, has a "1" signal on it, and these two "1" signals applied to AND circuit CF provide a zero signal at the output of the AND circuit CF which is applied to inverter blocks E1 to EN. The output of each of the pre-drive blocks E1 to EN thus is "1", which is desired. The -SCAN C signal is at this time "1" and remains "1" until a testing operation is desired. When latch L flips so that a "1" signal exists on the Q terminal, the conditions of the AA to AG, CF and E1 to EN circuits change to the opposite values so that at this time a zero signal exists on all of the outputs of pre...