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Browse Prior Art Database

Partial Parity Checking for Control Logic

IP.com Disclosure Number: IPCOM000047098D
Original Publication Date: 1983-Sep-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 43K

Publishing Venue

IBM

Related People

Nantt, DD: AUTHOR [+3]

Abstract

This article describes a method of providing partial error detection in the control logic of a processor, with very little overhead. In the processing unit of a processor, the control logic must decode the operation codes and decode control sequencer clocks. The decodes of these must control various signals that control the gating and clocking of registers in the data flow of the processor. At some sequencer decode times of an instruction, the outputs are a function of other signals, such as decodes of the operation code as well as control sequencer. If these final decodes are mutually exclusive, then there is no difficulty in predicting the final parity of the outputs.

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Partial Parity Checking for Control Logic

This article describes a method of providing partial error detection in the control logic of a processor, with very little overhead. In the processing unit of a processor, the control logic must decode the operation codes and decode control sequencer clocks. The decodes of these must control various signals that control the gating and clocking of registers in the data flow of the processor. At some sequencer decode times of an instruction, the outputs are a function of other signals, such as decodes of the operation code as well as control sequencer. If these final decodes are mutually exclusive, then there is no difficulty in predicting the final parity of the outputs. If the decodes of the signals can overlap such that more than one can be active at one time and if some of the outputs are controlled by one decode and others are a function of another, it may not be possible to easily determine the parity of the outputs. If implemented in a programmable logic array (PLA) the control logic is normally composed of an AND array that produces product terms, an OR array to provide control output signals which are logical sums of different combinations of the product terms, and output latches for holding the control output signals valid during the next control cycle. On the average only half the control operation and sequencer decodes will generate odd parity on the set of control outputs. The other half will produce a set of c...