Browse Prior Art Database

Edge-Triggered LSSD Compatible Set/Reset Latch

IP.com Disclosure Number: IPCOM000047153D
Original Publication Date: 1983-Oct-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 50K

Publishing Venue

IBM

Related People

Farrell, RH: AUTHOR [+2]

Abstract

This latch circuit is useful in applications where a trailing edge sensitive set-reset latch is desired. This latch is compatible with the Level Sensitive Scan Design (LSSD) groundrules set forth in a technical paper by Eichelberger, et al., entitled "A Logic Design Structure For LSI Testability" and appearing at pages 462-467 of the June 1977 Proceedings of 14th Design Automation Conference . Fig. 1 shows the circuit diagram, and Fig. 2 shows a typical timing diagram for same. A set pulse starts at time A. The L2 latch B clock turns off, causing the L2 latch to hold, and then the L1 latch is set. At time B on the trailing edge of the set pulse, the L2 latch B clock is turned on, causing the data from the L1 latch to be flushed to the L2 latch outputs. Thus, the latch is set on the trailing edge of the set pulse.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 93% of the total text.

Page 1 of 2

Edge-Triggered LSSD Compatible Set/Reset Latch

This latch circuit is useful in applications where a trailing edge sensitive set- reset latch is desired. This latch is compatible with the Level Sensitive Scan Design (LSSD) groundrules set forth in a technical paper by Eichelberger, et al., entitled "A Logic Design Structure For LSI Testability" and appearing at pages 462-467 of the June 1977 Proceedings of 14th Design Automation Conference . Fig. 1 shows the circuit diagram, and Fig. 2 shows a typical timing diagram for same. A set pulse starts at time A. The L2 latch B clock turns off, causing the L2 latch to hold, and then the L1 latch is set. At time B on the trailing edge of the set pulse, the L2 latch B clock is turned on, causing the data from the L1 latch to be flushed to the L2 latch outputs. Thus, the latch is set on the trailing edge of the set pulse. The reset pulse starts at time C. The L2 latch B clock is turned off, causing the L2 latch to hold and then the L1 latch is reset. At time D, the reset pulse goes off, causing the L2 B clock to turn on. This causes the data on the L1 latch outputs to be flushed through to the L2 latch outputs. Thus, the LZ latch is reset on the trailing edge of the reset pulse. The -B clock is always held inactive (+), the +C clock is always held active (+), and the +A clock is held inactive (-) when the logic is not in a scan mode. During scan mode, the -B clock controls the L2 latch B clock input, while the set and reset...