Browse Prior Art Database

I/O Storage Unit and Library Commands for Same

IP.com Disclosure Number: IPCOM000047154D
Original Publication Date: 1983-Oct-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 3 page(s) / 54K

Publishing Venue

IBM

Related People

Baker, ED: AUTHOR [+2]

Abstract

An I/O storage unit is described for increasing the performance of the operating system in a host processor to which the I/O storage unit is attached. An I/O storage unit 10 is coupled to the I/O channel bus of a host processor 11 in the same manner as other I/O devices 12. The processor 11 is assumed to be an IBM Series/1-type processor, and the operations set forth herein are described in terms of the Series/1 architecture. The I/O storage unit 10 includes a random-access memory (RAM) storage unit 13 for storing processor transients, terminal screen data, overlays, and so forth, which would otherwise need to be stored in and would take up considerable space in the processor main storage unit 16.

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I/O Storage Unit and Library Commands for Same

An I/O storage unit is described for increasing the performance of the operating system in a host processor to which the I/O storage unit is attached. An I/O storage unit 10 is coupled to the I/O channel bus of a host processor 11 in the same manner as other I/O devices 12. The processor 11 is assumed to be an IBM Series/1-type processor, and the operations set forth herein are described in terms of the Series/1 architecture. The I/O storage unit 10 includes a random- access memory (RAM) storage unit 13 for storing processor transients, terminal screen data, overlays, and so forth, which would otherwise need to be stored in and would take up considerable space in the processor main storage unit 16. In the case of smaller processor systems, there may not be sufficient main storage capacity to store such additional items, in which case such items would need to be stored in a peripheral disk or diskette unit connected to the I/O channel bus. The I/O storage unit 10 provides a substitute for such a disk or diskette unit and has a substantially faster overall data transfer rate than does such disk or diskette unit. Data is transferred between the processor 11 and the RAM storage 13 by way of the I/O channel bus, a data register 14 and a microprocessor bus
15. In the case of transients, terminal screens, overlays, etc., these transfers are performed into and out of the processor main storage unit 16 in a cycle steal mode. Cycle steal address register 17 provides the main storage address, and RAM address counter 18 provides the RAM storage address. In each case, the address value is incremented by one count as each byte of data is transferred. For the main storage address, this is accomplished by incrementing a cycle steal address counter 19 and loading the updated contents thereof into the address register 17. The operation of the I/O storage unit 10 is controlled by a microprocessor 20 and control microcode located in microprocessor storage 21. For any given data transfer operation, a byte counter 22 is initially loaded with a count value corresponding to the number of bytes to be transferred. Byte counter 22 is decremented as each byte of data is transferred, and when it reaches a count of zero, it signals the microprocessor 20 to tell it that the data transfer operation has been completed. The normal way of initiating a Series/1 cycle steal data transfer operation is to first transfer an eight-word device control block (DCB) from the processor 11 to the I/O unit. This device control block contains such items as a co...