Browse Prior Art Database

Multiplex Interface Control in a Closed-Ring Network

IP.com Disclosure Number: IPCOM000047161D
Original Publication Date: 1983-Oct-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 3 page(s) / 77K

Publishing Venue

IBM

Related People

Volk, JR: AUTHOR

Abstract

In the ring structured peer-to-peer communications network environment exemplified in Fig. 1, host data processing systems (in the illustration, systems associated with ring stations A, B, C and D; although a much larger number of systems and stations could easily be accommodated) intercommunicate as peers through identical ring adapter circuits termed ring communication controllers (RCCs). As suggested at station A, each RCC has an input port 1 for receiving information from the ring (R), an output port 2 for transferring information to the ring, and signal processing circuits indicated at 3.

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Multiplex Interface Control in a Closed-Ring Network

In the ring structured peer-to-peer communications network environment exemplified in Fig. 1, host data processing systems (in the illustration, systems associated with ring stations A, B, C and D; although a much larger number of systems and stations could easily be accommodated) intercommunicate as peers through identical ring adapter circuits termed ring communication controllers (RCCs). As suggested at station A, each RCC has an input port 1 for receiving information from the ring (R), an output port 2 for transferring information to the ring, and signal processing circuits indicated at 3. The circuits 3 include receiving/demodulating circuits 6, modulating/transmitting circuits 7, steering circuits 8 for selectively routing demodulated signals to associated host processing equipment and a variable delay path in series with the ring, selection circuits 9 for selectively transferring signals to ring output circuits 7 from either a local buffer source or the series path, a variable depth (FIFO) pass through buffer 10 in the series path for storing ring traffic enroute from steering circuits 8 to selection circuits 9, an input buffer 11 for storing incoming ring traffic for local processing, and an output buffer 12 for storing local origin messages for output transmission to the ring. Under control of microprocessor 13, the foregoing RCC circuits operate asynchronously to local processing equipment embodied in host system CPU 14 and its store 15. Communications between the host system and buffers 11 and 12 may be conducted asynchronously to host CPU operations via subchannels of host system I/O channel 16. In this environment microprocessor 13 and discrete hardware controls 19 orchestrate operations of the RCC under higher level supervision by host software. Controls 19 direct operations of elements 8, 9, 11 and 12 asynchronously to microprocessor operations. This allows these elements to operate simultaneously with the microprocessor without special priority logic for interrupting the microprocessor or overly complex software for resolving contentions for microprocessor service. Fig. 2 illustrates details of controls 19 (MIC (Multiplex Interface Controller)), and their relation to the microprocessor and host systems, and to RCC elements 8, 9, 11 and 12 (FEQ (Front End Queue) element 10 has its own discrete controls (not shown)). Controls 19 comprise a command latching section 19A, a timing section 19B and a sequence controlling section 19C. Section 19A receives and latches command signal functions presented by either the microprocessor, the host system or RCC receiver circuit 6. Section 19C reacts to signals presented by sections 19A and 19B, and develops signals for asynchronously controlling operations of buffer elements 11 and 12 relative to the ring, the microprocessor and the host system. Input buffer element 11 consists of a storage matrix section 11A, input gating secti...