Browse Prior Art Database

Programmable Data Formatting and Compacting Function

IP.com Disclosure Number: IPCOM000047176D
Original Publication Date: 1983-Oct-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 3 page(s) / 46K

Publishing Venue

IBM

Related People

Anemojanis, E: AUTHOR

Abstract

This article describes a data storage compaction and transfer method whereby only data required for the next level of operation need be transmitted. The apparatus basically comprises a programmable width data-out register 10 including decrementer means for counting the bits in the register. A data buffer 11 coupled to the data-out register contains significantly greater bits than the data-out register and also includes decrementing means for counting the bits in the buffer data field. A means for transferring in parallel bits from the data buffer which are equal in number to those in the data-out register and transferring the bits out of the data-out register while simultaneously resetting the decrementer in the data-out register to zero.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 39% of the total text.

Page 1 of 3

Programmable Data Formatting and Compacting Function

This article describes a data storage compaction and transfer method whereby only data required for the next level of operation need be transmitted. The apparatus basically comprises a programmable width data-out register 10 including decrementer means for counting the bits in the register. A data buffer 11 coupled to the data-out register contains significantly greater bits than the data-out register and also includes decrementing means for counting the bits in the buffer data field. A means for transferring in parallel bits from the data buffer which are equal in number to those in the data-out register and transferring the bits out of the data-out register while simultaneously resetting the decrementer in the data-out register to zero. When this is accomplished, means used for transferring the bits from the data buffer is deactivated and suitable circuits for serially transferring bits out of the data buffer and resetting the decrementer means in the data buffer are reset to zero. Finally, there are provided means for deactivating the apparatus used for serially transferring the bits from the data buffer and reactivating the means for transferring them in parallel from the data buffer when both decrementers are returned to zero. In the present apparatus the field of the data buffer 11 is assumed to be 24 bits, the data is assumed to consist of three islands with 8 bits each while the CPU 12 coupled to the data-out register 10, is capable of only handling 16-bit words. There are several different ways of utilizing the apparatus. In mode 1, the part number program will load the N width register 13 with the data buffer number 24 which is the extent of the data of the buffer data field. The X width register 14 is loaded with the number 16 which is the size of the field transferable to the CPU. These numbers are also loaded into the corresponding counters 15 and 16. When the transfer from the buffer register is initiated, control logic will start the operation by shifting in the gated bit from the decoder 17 into the data-out register 10 through the serial data input. Both N and X (15 and 16) counters are decremented. The loop repeats until the X counter is down to zero, the clock is stopped and requests transfer to the CPU. The X counter is now reloaded with the value 16 from the X width register. The CPU acknowledges obtaining the data and causes the clock to start. The remaining bits have now shifted into the data-out register which will set the N counter borrow signal, causing the clock to stop. The buffer SAR counter 20 is now incremented, and the N counter reloaded with the number 24. After a suitable delay, the sequence continues until all of the information from the data buffer 11 is transferred into the CPU 12 through the data-out register 10. In the case where the number N is greater than the number X, the N counter borrow will increment the SRA counter and the X counter...