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Gated Register Pattern Generator for High Speed RAM Testing

IP.com Disclosure Number: IPCOM000047178D
Original Publication Date: 1983-Oct-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 43K

Publishing Venue

IBM

Related People

Prilik, RJ: AUTHOR

Abstract

This is a gated register pattern generator for high speed random-access memory (RAM) testing which uses level sensitive scan design (LSSD) scan for high speed array testing and a high speed pattern generator without microcode or pipeline delays and circuit speed limitations, thus replacing present costly test techniques. A high speed RAM test method is shown in the figure. A plurality of registers 10 is loaded via a scan path 11. Each of the registers 10 contains read, write and control data and address information, i.e., a register stack. A multiplexer 12, controlled by a gated oscillator 13, selects the device under test (DUT), addresses, data and control information at high speed without microcode.

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Gated Register Pattern Generator for High Speed RAM Testing

This is a gated register pattern generator for high speed random-access memory (RAM) testing which uses level sensitive scan design (LSSD) scan for high speed array testing and a high speed pattern generator without microcode or pipeline delays and circuit speed limitations, thus replacing present costly test techniques. A high speed RAM test method is shown in the figure. A plurality of registers 10 is loaded via a scan path 11. Each of the registers 10 contains read, write and control data and address information, i.e., a register stack. A multiplexer 12, controlled by a gated oscillator 13, selects the device under test (DUT), addresses, data and control information at high speed without microcode. Multiplexer 12 is only a simple AND/OR-type circuit and requires only a few logic gates to select a register and apply inputs to the array under test 14. Under the best possible conditions a self-contained array timing (SCAT) signal for line 16 strobes all inputs into the array under test 14 at a specific time and stores their outputs via a second multiplexer 15 into a series of output registers 17 at a strobe error time rate established on line 18. In a worse case, the gated oscillator 13 can apply non-self-contained array timing to the device under test 14 as well as error strobe and register select signals. A serial scan path "scan out" on line 19 passes the DUT response back to the CPU or to a general a...