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Smooth Switching DC Circuit

IP.com Disclosure Number: IPCOM000047181D
Original Publication Date: 1983-Oct-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 31K

Publishing Venue

IBM

Related People

Coderre, Y: AUTHOR

Abstract

A combined damping and delay control circuit for controlling (a) a voltage level that drives a peak sensitive device such as ROS, RAM, etc., (b) a signal that needs to be delayed (lag or lead) from the main voltage level under control, and (c) voltage switching from relay point contact which tends to be noisy and spurious ensures smooth switching of DC voltage from ground level and comprises a pair of networks. As per the drawing, Network A is an RC damping circuit interconnected with Network B, a delay circuit. Capacitor C1, in combination with resistors R3 and R4, limits the rise and fall of the +25 V (supply) signal to ensure that no pulse smaller than 100 ns can be switched. Resistors R3 and R4 also operate to limit the current to 1A across the relay points.

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Smooth Switching DC Circuit

A combined damping and delay control circuit for controlling
(a) a voltage level that drives a peak sensitive device

such as ROS, RAM, etc., (b) a signal that needs to be delayed (lag or lead) from the main voltage level under control, and (c) voltage switching from relay point contact which tends to be noisy and spurious

ensures smooth switching of DC voltage from ground

level and comprises a pair of networks. As per the drawing, Network A is an RC damping circuit interconnected with Network B, a delay circuit. Capacitor C1, in combination with resistors R3 and R4, limits the rise and fall of the +25 V (supply) signal to ensure that no pulse smaller than 100 ns can be switched. Resistors R3 and R4 also operate to limit the current to 1A across the relay points.

Diode D1 operates as a protective diode to protect the "+VPP ON" sink circuit in the event that R2 becomes open. For example, the control circuit can be used for controlling a 25 V power supply level and ensuring that steady state has been achieved prior to gating controlling logics at VCC, and making sure that the time between 10% and 90% of 25 V is greater than 100 ns to prevent spike damage of the device under control: Vs = 25 V R1 = 2.0 K R3 = 20 C1 = 3.3 f Vcc = 5 V R2 = 510 R4 = 24 C2 = 8.2 f R1 and R2 operate as a divider network to provide (+5 V) to the Vcc line after C2 has been charged through R1, with a time contact of T = R1C2 = 16 ms. R2 also provides a discharge p...