Browse Prior Art Database

Elimination of Shorts Between Metallization Levels

IP.com Disclosure Number: IPCOM000047199D
Original Publication Date: 1983-Oct-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 36K

Publishing Venue

IBM

Related People

Geldermans, P: AUTHOR

Abstract

A method for the elimination of unwanted interlevel metallization shorts through a dielectric insulator is disclosed. As shown in the figure, a portion of a carrier for an integrated circuit chip is composed of a ceramic substrate 1 having a metallized via therein which terminates at a contact pad 3. A ground plane 4 overlies a portion of the substrate surface separate from the contact pad 3. A dielectric insulator 5 overlies the ground plane 4 and the surface of the substrate, and has a metallized via 6 therethrough. A conductor line 7 overlies the surface of the insulator 5, and makes contact to the pad 3 through the metallized via 6.

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Elimination of Shorts Between Metallization Levels

A method for the elimination of unwanted interlevel metallization shorts through a dielectric insulator is disclosed. As shown in the figure, a portion of a carrier for an integrated circuit chip is composed of a ceramic substrate 1 having a metallized via therein which terminates at a contact pad 3. A ground plane 4 overlies a portion of the substrate surface separate from the contact pad 3. A dielectric insulator 5 overlies the ground plane 4 and the surface of the substrate, and has a metallized via 6 therethrough. A conductor line 7 overlies the surface of the insulator 5, and makes contact to the pad 3 through the metallized via 6. In the fabrication of the carrier an irreparable short 8 can be formed by metallization of an unintentional defect in the insulator 5, such as a pore, during the formation of the conductor line 7. A solution to this problem is to remove the ground plane wherever it underlies the conductor lines. To do this requires only that the negative of the conductor line pattern be added to the mask used to delineate the ground plane while ensuring that the ground plane remains continuous. This additional delineation of the ground plane will not significantly change the impedance of the carrier while greatly reducing the incidence of interlevel shorts.

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