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Compatible Circuits Implemented in DDL and TTL Technology

IP.com Disclosure Number: IPCOM000047200D
Original Publication Date: 1983-Oct-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 69K

Publishing Venue

IBM

Related People

Gani, VL: AUTHOR [+3]

Abstract

This is a technique for providing compatible logic levels for diode-diode logic (DDL) and transistor-transistor logic (TTL). Fig. 1 illustrates a TTL circuit in which transistor TIN is flexible to receive both internal and external logic voltage swings. Internal signals are in the order of zero to -1.2 volts. External signals in the order of -0.8 to -2.0 volts can be received by means of shorting the isolated bases to the common collector, as shown by dotted lines. The same circuit function performed by the TTL circuit in Fig. 1 is performed by the DDL circuit in Fig. 2. By replacing transistor TIN with low barrier Schottky barrier diodes (SBDs), the Fig. 2 circuit provides a TTL compatible logic circuit with better speed.

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Compatible Circuits Implemented in DDL and TTL Technology

This is a technique for providing compatible logic levels for diode-diode logic (DDL) and transistor-transistor logic (TTL). Fig. 1 illustrates a TTL circuit in which transistor TIN is flexible to receive both internal and external logic voltage swings. Internal signals are in the order of zero to -1.2 volts. External signals in the order of -0.8 to -2.0 volts can be received by means of shorting the isolated bases to the common collector, as shown by dotted lines. The same circuit function performed by the TTL circuit in Fig. 1 is performed by the DDL circuit in Fig. 2. By replacing transistor TIN with low barrier Schottky barrier diodes (SBDs), the Fig. 2 circuit provides a TTL compatible logic circuit with better speed. To achieve a transparent chip with the DDL circuit, additional diodes (B- C or E-B) are required to receive external signals. These diodes are required to shift external signals of -2.0 to -0.8 volt to internal signal levels of zero to -1.2 volts. This is accomplished by diode D3 which receives a signal driven by an emitter follower at logic levels of -2.0 to -0.8 volt and shifts this level to the internal voltage levels. The use of an E-B diode for external level shift introduces an additional capacitance C ISO at the base of the transistor output device TOUT and slows down the circuit significantly. The use of a B-C diode with higher diffusion capacitance may speed up the circuit, but...