Browse Prior Art Database

CMOS (N-Well) Master Image Chip

IP.com Disclosure Number: IPCOM000047223D
Original Publication Date: 1983-Oct-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 32K

Publishing Venue

IBM

Related People

Bansal, JP: AUTHOR

Abstract

A master slice layout arrangement is disclosed to enable the subsequent formation of N-channel and P-channel FET devices which can be interconnected to create complementary MOS circuits. Fig. 1 is an overall view of the general chip layout of diffusions in the semiconductor substrate 10. Fig. 2 is a cross-sectional view along the section line X-X' of Fig. 1, showing that the semiconductor chip 10 is a P-type doped substrate within which have been diffused vertical columns 20 of N-type conductivity dopant so as to form N-well diffusions for the subsequent location of P-channel FET devices. The arrangement of the vertical columns of N-type diffusions allows for the placement of N-channel FET devices in a P-type substrate between the adjacent N-type diffusion wells 20.

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CMOS (N-Well) Master Image Chip

A master slice layout arrangement is disclosed to enable the subsequent formation of N-channel and P-channel FET devices which can be interconnected to create complementary MOS circuits. Fig. 1 is an overall view of the general chip layout of diffusions in the semiconductor substrate 10. Fig. 2 is a cross- sectional view along the section line X-X' of Fig. 1, showing that the semiconductor chip 10 is a P-type doped substrate within which have been diffused vertical columns 20 of N-type conductivity dopant so as to form N-well diffusions for the subsequent location of P-channel FET devices. The arrangement of the vertical columns of N-type diffusions allows for the placement of N-channel FET devices in a P-type substrate between the adjacent N-type diffusion wells 20. This is indicated by the rectangular regions 30, which show the P-type region within which N-channel FET devices can be subsequently formed. By virtue of their close proximity, the N-channel FET devices formed in the regions 30 can be inter connected with the P-channel FET devices formed in the regions 20 so as to make complementary MOS circuits. Reference is now made to Fig. 3 which illustrates the magnified view of the layout shown in Fig. 1, wherein an N-type well 20 is shown as a first column and the N-channel regions 30 on each side of the N-well 20 are shown occupying the P-type substrate regions. The layout diagram of Fig. 3 shows how a four-way NOR circuit can be formed in CMOS technology using N-channel devices formed in the region 30 and P-channel devices formed in the region 20. Still further, a four-way NAND function is shown being formed in CMOS technology by means of N-channel devices formed in the region 30 and P-channel devices formed in the region 20. A circuit...