Browse Prior Art Database

Low Drain High/Low Logic-Controlled Voltage Selector Circuit

IP.com Disclosure Number: IPCOM000047228D
Original Publication Date: 1983-Oct-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 3 page(s) / 34K

Publishing Venue

IBM

Related People

Hoffman, CR: AUTHOR

Abstract

Electrically alterable memory systems are increasingly important for digital applications. Programming and erasing of electrically alterable semiconductor devices require relatively high voltages - on the order of 18 to 25 volts in general. However, ordinary logic levels of approximately 5 volts are normally supplied. In order to generate the high voltage levels, charge pumps consisting of capacitive bootstrap circuits and switches are normally employed to boost the voltage. However, such devices have very low current supply capabilities. Therefore, very small current drain circuitry must be employed. The high voltage is usually required only during the data altering operation, and some means of switching under logic control between the high voltage and the logic level voltage must be employed.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 51% of the total text.

Page 1 of 3

Low Drain High/Low Logic-Controlled Voltage Selector Circuit

Electrically alterable memory systems are increasingly important for digital applications. Programming and erasing of electrically alterable semiconductor devices require relatively high voltages - on the order of 18 to 25 volts in general. However, ordinary logic levels of approximately 5 volts are normally supplied. In order to generate the high voltage levels, charge pumps consisting of capacitive bootstrap circuits and switches are normally employed to boost the voltage. However, such devices have very low current supply capabilities. Therefore, very small current drain circuitry must be employed. The high voltage is usually required only during the data altering operation, and some means of switching under logic control between the high voltage and the logic level voltage must be employed. The figure discloses a simple circuit having very low current drain characteristics that easily switches between the high and low voltage levels for such applications. In Fig. 1, normal circuit operation is to supply at the output node 1 an output supply voltage. This is normally the logic level supply VDD applied at node 2. During normal logic circuit operation, the charge pumps apply at node 3, denoted VCP, will be 0. Under these circumstances, the voltage follower network, consisting of devices Q1 through Q5 will be seen as a high impedance network at the output node 1 since Q5, will be off. Q5 is an enhancement-mode FET device and is off because its gate is grounded through the depletion-mode device Q4 with VCP at node 3 at 0 volts. During normal logic mode operation, the input voltage VIN on node 4 is also at ground and this allows the gate of device Q8 to be pulled up to the logic supply VDD at node 2 through the depletion-mode device Q6, as shown. The output voltage at node 1 is therefore effectively the logic voltage VDD in this mode of operation. When a memory erase or write operation is required, VIN on node 4 will be positive and the charge pump voltage VCP will be at the high voltage required and applied to node 3. When the node 3 voltage is positive, the voltage follower network Q1 - Q5 will operate at an output voltage generated in response to the reference voltage applied at the Q1 gate. Because the input voltage at node 4 is positive, the gate of device Q8 will be at ground because device Q7 will drain the supply provided by device Q6. Even though Q8 is a depletion-mode device, its gate will be sufficiently below its source voltage VDD to turn Q8 off and prevent any current loading on the charge pump supply coming through device Q5. When the charge pump supply at node 3 is at a high level, device Q4 serves as a load device for the differential pair of en...