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Gain Control Circuit for Optical Scanner

IP.com Disclosure Number: IPCOM000047230D
Original Publication Date: 1983-Oct-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 3 page(s) / 65K

Publishing Venue

IBM

Related People

Cato, RT: AUTHOR [+2]

Abstract

This article describes an automatic gain control circuit for a photomultiplier tube (PMT) in an optical scanner of the type using a holographic disc. The gain control circuit includes an adjustment to compensate for differences in the diagnostic label and the diagnostic facet from one scanner to the next. A greater lock-out voltage is established for light average signals than for dark average signals. Fig. 1 is a general block diagram of the relevant portions of an optical scanner circuit. PMT circuits 10 provide an electrical signal which is amplified before being applied to an AND gate 12, a white follower circuit 14 and a black follower circuit 16. The outputs of VWF and VBF circuits 14 and 16 are applied to a lock-out circuit 18 which generates a threshold voltage that is applied to AND gate 12.

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Gain Control Circuit for Optical Scanner

This article describes an automatic gain control circuit for a photomultiplier tube (PMT) in an optical scanner of the type using a holographic disc. The gain control circuit includes an adjustment to compensate for differences in the diagnostic label and the diagnostic facet from one scanner to the next. A greater lock-out voltage is established for light average signals than for dark average signals. Fig. 1 is a general block diagram of the relevant portions of an optical scanner circuit. PMT circuits 10 provide an electrical signal which is amplified before being applied to an AND gate 12, a white follower circuit 14 and a black follower circuit 16. The outputs of VWF and VBF circuits 14 and 16 are applied to a lock-out circuit 18 which generates a threshold voltage that is applied to AND gate 12. The selective gating of And gate 12 generates a digitized or squared video signal. The output of AND gate 12 is applied to an automatic gain control (AGC) circuit 20. This circuit will be described in more detail later. Other inputs to the AGC circuit 20 include a "shutter open" signal and a voltage VD which is generated when the diagnostic facet is being scanned. Rotation sensor 11 generates this signal. Fig. 2 shows the lock-out circuit 18 in detail. The circuit includes NPN transistors 22A and 22B in a common emitter configuration 22. Transistor 22B is driven by VBF . Transistor 22A is driven by VWF . A constant current circuit 24 is connected between the common emitter junction and ground. The collector signal on transistor 22B is applied to a level shifting circuit 26 at one input of AND gate 12. A circuit 28 temporarily increases the lock-out voltage when the diagnostic label is being scanned. This circuit includes a potentiometer 30 for establishing an initial set point. When the diagnostic facet is scanned, the logic level signal VD goes high, saturating transistor 32. This increases the voltage drop across resistor 34 which, in turn, requires that the black follower voltage be lower than normal before transistor 22 will be gated off. When transistor 22 is gated off, the output of level shifte...