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Performance Selection Method Based on Current Measurement in LSI Chips

IP.com Disclosure Number: IPCOM000047238D
Original Publication Date: 1983-Oct-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 1 page(s) / 13K

Publishing Venue

IBM

Related People

Williams, RR: AUTHOR

Abstract

LSI logic circuits exhibit a large 'delay multiplier' between nominal performance and worst-case performance. A typical multiplier is 2, although, in general, this is dependent on technology (bipolar, FET, and so forth) and specified control of various process parameters (W/L ratios, threshold mobilities in the case of FETs). Also, the probability density function of delay values for a logic block implies that relatively few cases extend to the 'tail' of the distribution to cause this large delay multiplier. It is well known that there is a high correlation between current and performance. This article describes a simple method of selection based on current measurement in LSI chips that permits discarding the relatively few cases on the tail of the distribution.

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Performance Selection Method Based on Current Measurement in LSI Chips

LSI logic circuits exhibit a large 'delay multiplier' between nominal performance and worst-case performance. A typical multiplier is 2, although, in general, this is dependent on technology (bipolar, FET, and so forth) and specified control of various process parameters (W/L ratios, threshold mobilities in the case of FETs). Also, the probability density function of delay values for a logic block implies that relatively few cases extend to the 'tail' of the distribution to cause this large delay multiplier. It is well known that there is a high correlation between current and performance. This article describes a simple method of selection based on current measurement in LSI chips that permits discarding the relatively few cases on the tail of the distribution. It is presently a normal part of chip testing to measure chip current immediately following power-on to weed out parts containing catastrophic short circuits or chips in which there is no current. To use this selection method, a series of input changes, or patterns, must subsequently be run into the chip in such a way as to initialize all memory elements on the chip. In this state, there will be no nets on the chip whose logic condition is unknown. The current is to be measured in this state and compared with a calculated chip current value for the chip in this same state. The chip is to be rejected if the current measurement is lower than the calculated value. The chip current calculation can be done automatically with the aid of software digital simulation programs to...