Browse Prior Art Database

Multiple Counter Logic Circuit

IP.com Disclosure Number: IPCOM000047241D
Original Publication Date: 1983-Oct-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 26K

Publishing Venue

IBM

Related People

Dix, GL: AUTHOR

Abstract

This circuit minimizes the logic required for implementing multiple counters which do not require simultaneous increment or decrement. It can be advantageously implemented in a multiport RAM (random-access memory) in which each RAM port has an independent address, but only one address can be presented to the RAM during a given cycle. The multiple counter structure, shown in the figure, implements three separate counters. The counter values are normally stored in registers 1, 2, and 3. When one of the counters is accessed, its value is transferred to block 4 either directly or via selection block 6. The incremented or decremented value will appear on the output of block 5, and the updated value is stored back in the originating block.

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Multiple Counter Logic Circuit

This circuit minimizes the logic required for implementing multiple counters which do not require simultaneous increment or decrement. It can be advantageously implemented in a multiport RAM (random-access memory) in which each RAM port has an independent address, but only one address can be presented to the RAM during a given cycle. The multiple counter structure, shown in the figure, implements three separate counters. The counter values are normally stored in registers 1, 2, and 3. When one of the counters is accessed, its value is transferred to block 4 either directly or via selection block 6. The incremented or decremented value will appear on the output of block 5, and the updated value is stored back in the originating block. The number of counters can be increased by adding registers and additional selector inputs on selection block 6. The primary advantage is that less logic is required than if separate counters were implemented because blocks 4 and 5 are shared among all the counters. In the application of RAM addressing, there are some additional advantages. The RAM address can be taken directly from the output of block 4 and no external selectors are required. There is also a testability advantage since the address is observable on the LSSD (level-sensitive scan design) scan string.

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