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Simple Fabrication Technique to Implement a Buried N-Type Grid Under a Memory Array for Protection Against Radiation-Induced Soft-Errors

IP.com Disclosure Number: IPCOM000047283D
Original Publication Date: 1983-Oct-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 3 page(s) / 69K

Publishing Venue

IBM

Related People

Chao, HH: AUTHOR [+3]

Abstract

A fabrication process is described for producing a buried n-grid located in selected desired places below the Si surface of a high density dynamic random-access memory (DRAM) to protect circuits and devices located on the surface from collecting excess charge generated in the substrate by ionizing radiation. Using the process described, the grid can be implemented with no extra masking steps for DRAM circuits using diffusion storage and/or HI-C-type storage enhancements. The fabrication follows a standard semi-ROX, no-ROX or full-ROX process up to the point where device active areas have been defined and the thick field and thin gate oxides grown. Photoresist is then applied and defined using a single combined HI-C/n-grid mask. Diffusion store and/or HI-C-type implants are then performed using the resist as an implant mask.

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Simple Fabrication Technique to Implement a Buried N-Type Grid Under a Memory Array for Protection Against Radiation-Induced Soft-Errors

A fabrication process is described for producing a buried n-grid located in selected desired places below the Si surface of a high density dynamic random-access memory (DRAM) to protect circuits and devices located on the surface from collecting excess charge generated in the substrate by ionizing radiation. Using the process described, the grid can be implemented with no extra masking steps for DRAM circuits using diffusion storage and/or HI-C-type storage enhancements. The fabrication follows a standard semi-ROX, no-ROX or full-ROX process up to the point where device active areas have been defined and the thick field and thin gate oxides grown. Photoresist is then applied and defined using a single combined HI-C/n-grid mask.

Diffusion store and/or HI-C-type implants are then performed using the resist as an implant mask. Al is then evaporated and lifted off using this same patterned resist layer. A high energy boron implant is then performed placing the boron deep below the surface in areas where the Al was not present and less deep below the surface where Al was left. This results in the structure illustrated in Fig. 1. The Al is then stripped off, and the boron driven-in. A high energy phosphorous implant is then performed which places the peak concentration of the phosphorous coincident with the deeper peak in the boron concentration. A buried n-region results in the substrates wherever Al was present, and boron compensates this layer in all other regions, resulting in no n-layer below where Al was not present. Then normal processing resumes including threshold adjust implants, polysilicon definition, source/drain implantation and drive-in, passivation and metallization to form the completed structure. This scheme also allows the buried p+ layer to come up close to the surface in selected thick oxide areas, as C and D of Fig. 2. This may be used to enhance the isolation between two n-type regions or two storage regions or may be used to locally increase the field threshold voltage under high voltage (boosted) lines. Thus, each region shown in Fig. 2 has the following characteristics which may be achieved using this process scheme: REGION A: An n+ region such as a Vdd or GROUND node which can tolerate large junction capacitance due to the shallow buried p+ region or requires the protection from collected excess charge provided by the buried n-layer directly beneath it. REGION B: An n+ region such as a bitline or other node which requires its junction capacitance to be minimized. Therefore, the p+ layer must be made deep in this region. This region is still protected from exces...