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Low Temperature Logic Testing

IP.com Disclosure Number: IPCOM000047286D
Original Publication Date: 1983-Oct-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 50K

Publishing Venue

IBM

Related People

Herrell, DJ: AUTHOR

Abstract

Designing Josephson logic chips so as to be operative without the inclusion of inverters, through the use of complementary logic, permits testing on the basis of the presence or absence of an AC signal and eliminates testing problems associated with discriminating between the various AC signal levels on chip circuits associated with long-line receivers. With logic designed without the use of inverters -- using complementary logic based around true and complementary output from latches in conjunction with AND and OR then the amplifier has merely to discriminate between the presence and the absence of an AC signal (Fig. 1), about the zero base line (broken line, Fig. 1). This then allows: (1) Amplifier implementation with better margins. (2) Feasibility of better discrimination between signal (1) and noise (0) (e.g.

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Low Temperature Logic Testing

Designing Josephson logic chips so as to be operative without the inclusion of inverters, through the use of complementary logic, permits testing on the basis of the presence or absence of an AC signal and eliminates testing problems associated with discriminating between the various AC signal levels on chip circuits associated with long-line receivers. With logic designed without the use of inverters -- using complementary logic based around true and complementary output from latches in conjunction with AND and OR then the amplifier has merely to discriminate between the presence and the absence of an AC signal (Fig. 1), about the zero base line (broken line, Fig. 1).

This then allows: (1) Amplifier implementation with better margins. (2) Feasibility of better discrimination between

signal (1) and noise (0) (e.g., crosstalk, external).

(3) Amplifier design as narrow band around AC power

frequency to allow better rejection of noise. In the figures,

PI = primary input

PO = primary output

LLR = long-line receiver

I = inverter

SLR - short-line receiver In the more conventional circuit configuration (Fig. 2) with inverters, testing Josephson logic chips with DC signal levels leads to problems with interpreting primary outputs on chip circuits associated with long-line receivers. This leads to a need for a special DC-coupled discriminating amplifier where discrimination can be made between the various AC signal levels below or above the b...