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Write Gate With Control Current Coupled to the Storage Loop

IP.com Disclosure Number: IPCOM000047290D
Original Publication Date: 1983-Oct-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 37K

Publishing Venue

IBM

Related People

Anderson, CJ: AUTHOR

Abstract

Margins of the write gate in a Josephson storage latch are increased by coupling the control line of the write gate to the storage loop. In memory applications, coupling the DC bias lines to the memory storage loop may also be used to increase margins. The write gate and storage loop of the latch are shown in Fig. 1, where Q1 is the write gate, Ic is the control current, Ig is the gate current, LL is the storage loop inductance, LC is the inductance in the control time, and Lm is the coupling inductance. The threshold curve (solid line) in Fig. 2 is for a write gate with some current stored in the loop and the control current coupled only to the write gate.

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Write Gate With Control Current Coupled to the Storage Loop

Margins of the write gate in a Josephson storage latch are increased by coupling the control line of the write gate to the storage loop. In memory applications, coupling the DC bias lines to the memory storage loop may also be used to increase margins. The write gate and storage loop of the latch are shown in Fig. 1, where Q1 is the write gate, Ic is the control current, Ig is the gate current, LL is the storage loop inductance, LC is the inductance in the control time, and Lm is the coupling inductance. The threshold curve (solid line) in Fig. 2 is for a write gate with some current stored in the loop and the control current coupled only to the write gate. If the floor of the write gate is high due to parasitic inductances, the control current cannot erase the stored current because the control does not cross the threshold curve (see point A in Fig. 2). Coupling the control current to the storage loop as well as to the write gate suppresses the threshold curve, making the stored current easier to erase. The dashed curve in Fig. 2 is the same as the solid curve, only it has been suppressed by coupling the control current to the storage loop. Point A in Fig. 2 is now outside the threshold curve. The coupling of control current to the storage loop will also affect the write operation. The gate current Ig can also be coupled to the storage loop so that the suppression for both the erase and write operations...