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High Capacitance Dynamic Random-Access Memory Cell With Self-Aligned Storage Capacitor

IP.com Disclosure Number: IPCOM000047293D
Original Publication Date: 1983-Oct-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 61K

Publishing Venue

IBM

Related People

Chao, HH: AUTHOR [+3]

Abstract

Fig. 1 shows a high capacitance (Hi-C) memory cell for a dynamic RAM (random-access memory) to increase the storage capacitance per unit area. The storage capacitor has two major components: one related to the thin insulator 10, and the other to the N+/P+ junction 12. These N+/P+ regions created by Hi-C implants provide not only increased capacitance but also better isolation and reduced transient noise, although extra fabrication steps are required. The cell in Fig. 1 uses silicon dioxide 14 (SiO2) as the gate insulator and silicon nitride 16 on silicon dioxide 14 (Si3N4/SiO2) as the capacitor insulator. By doing so, the high dielectric material can be used to increase the storage capacitance and, on the other hand, the oxide can still be used as the gate insulator.

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High Capacitance Dynamic Random-Access Memory Cell With Self-Aligned Storage Capacitor

Fig. 1 shows a high capacitance (Hi-C) memory cell for a dynamic RAM (random-access memory) to increase the storage capacitance per unit area. The storage capacitor has two major components: one related to the thin insulator 10, and the other to the N+/P+ junction 12. These N+/P+ regions created by Hi- C implants provide not only increased capacitance but also better isolation and reduced transient noise, although extra fabrication steps are required. The cell in Fig. 1 uses silicon dioxide 14 (SiO2) as the gate insulator and silicon nitride 16 on silicon dioxide 14 (Si3N4/SiO2) as the capacitor insulator. By doing so, the high dielectric material can be used to increase the storage capacitance and, on the other hand, the oxide can still be used as the gate insulator. In realizing this structure, it is difficult to have N+/P+ 12 regions, insulators 14/16, and top capacitor 18 plates all self-aligned, as indicated in Fig. 1. A significant portion of capacitance, therefore, may be lost, and the values of different capacitors may be difficult to keep track of due to process variations. A method is described herein to fabricate the Hi-C memory cell with the N+/P+ regions 12 and the thin insulators 14/16 self-aligned to the edge of the top capacitor plates 18. Referring to Fig. 2A, the field isolation between cells is made in a standard NMOS process by using a nitride-on-oxide mask. After the nitride and oxide are removed, the insulator for the storage capacitor is formed, for example, 50 ~ thermal oxide 14 plus 150 ~ deposited nitride 16. Then a resist layer 20 is defined to shield the rest of the chip area from Hi-C implants, and a shallow N+ layer 22 and a deeper P+ layer 24 are implanted into the storage region of the cells. The N+ implant can be 95 KeV arsenic with a 4x1013/cm2 dose, and the P implant can be 100 KeV boron with a 2x1012/cm2 do...