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Avoiding Spurious Failure Indications in Testing Josephson Logic Chips

IP.com Disclosure Number: IPCOM000047294D
Original Publication Date: 1983-Oct-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Related People

Herrell, DJ: AUTHOR

Abstract

Designing Josephson logic chips for testability by directing all primary inputs to respective single input gates permits testing without the occurrence of the "double one problem" which might otherwise result in apparent failures in good chips. Testing of Josephson logic chips with DC inputs can potentially lead to the "double one problem" (Figs. 1 and 2). In this case a logic gate, such as a two-input OR receives two inputs directly from primary inputs (PIs). Since the controls are DC with respect to the AC power toggle frequency, there is a possible condition that with two ones presented to the PIs the operating point will fall below the 1,1 lobe and the gate will not switch. This leads to an error condition in testing -- the OR gate can behave like an exclusive OR.

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Avoiding Spurious Failure Indications in Testing Josephson Logic Chips

Designing Josephson logic chips for testability by directing all primary inputs to respective single input gates permits testing without the occurrence of the "double one problem" which might otherwise result in apparent failures in good chips. Testing of Josephson logic chips with DC inputs can potentially lead to the "double one problem" (Figs. 1 and 2). In this case a logic gate, such as a two-input OR receives two inputs directly from primary inputs (PIs). Since the controls are DC with respect to the AC power toggle frequency, there is a possible condition that with two ones presented to the PIs the operating point will fall below the 1,1 lobe and the gate will not switch. This leads to an error condition in testing -- the OR gate can behave like an exclusive OR. In normal operation (Ig before Ic) this condition will not arise. Thus "good" chips can test "bad" due to the "double one problem." This "double one problem" is obviated by requiring that all PIs to the chip go to single input gates. Examples of single input gates are: (1) a long line receiver, and (2) single or double turn of the control on an isolator

(Figs. 3 and 4). (The double-turn option of Figs. 3 and 4 is preferred as it also ensures that chip-to-chip communication from a low current density chip to a high current density chip can be done without a special driver.)

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