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Bit Line Transfer Efficiency Measurements at In-Line Testing

IP.com Disclosure Number: IPCOM000047325D
Original Publication Date: 1983-Nov-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Warren, MJ: AUTHOR

Abstract

This article describes a method for measuring the approximate transfer efficiency of dynamic memory cells using the DC testers that are used for in-line monitoring and characterization of devices. The charge present in a cell will not charge the bit line to the potential stored in the cell but only to a fraction of that voltage. Thus, the transfer efficiency of a given memory cell is defined as the efficiency with which voltage stored in a storage node can be transferred to a sense amplifier input. The measurement technique published in this article is performed on test sites or with slightly modified array structures. In Fig.

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Bit Line Transfer Efficiency Measurements at In-Line Testing

This article describes a method for measuring the approximate transfer efficiency of dynamic memory cells using the DC testers that are used for in-line monitoring and characterization of devices. The charge present in a cell will not charge the bit line to the potential stored in the cell but only to a fraction of that voltage. Thus, the transfer efficiency of a given memory cell is defined as the efficiency with which voltage stored in a storage node can be transferred to a sense amplifier input. The measurement technique published in this article is performed on test sites or with slightly modified array structures. In Fig. 1 there is shown an equivalent circuit of a modified array of cells connected to an equivalent circuit of a modified sense amplifier, where NCsn represents the storage capacitance of N cells, Cbl is the bit line capacitance, and Csa is the sense amplifier input capacitance. This equivalent circuit can be seen to be a capacitance divider and, at node X, the transconductance of the driver device will be reduced by the factor:

(Image Omitted)

In Fig. 2 there is shown the equivalent circuit of a reference device adjacent the array circuit. The measurement of transfer efficiency is performed by forcing drain currents through the bit line of the array and through the reference device X and measuring the gate voltages in both the bit line gate device and the reference device for two diff...