Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Memory Cell With Minimized Negative Resistance Effects

IP.com Disclosure Number: IPCOM000047329D
Original Publication Date: 1983-Nov-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 45K

Publishing Venue

IBM

Related People

Hargrove, MJ: AUTHOR [+2]

Abstract

A complementary transistor switch (CTS) memory cell has a layout which minimizes extrinsic resistance of the NPN base region by splitting the base contact between two P+ base diffusions coupled by a Schottky barrier diode contact. This minimization of the extrinsic base resistance decreases the negative dynamic resistance effects of the cell which is necessary for stable operation. The electrical circuit of the cell is shown in Fig. 1. The circuit includes first and second cross-coupled bipolar NPN transistors T1 and T2, respectively, each having a pair of dual emitters, first and second PNP transistors T3 and T4, respectively, and first and second Schottky barrier diodes D1 and D2, respectively. A cross-section of the layout of the half cell, i.e., devices T1, T3 and D1, is illustrated in Fig. 2. As seen in Fig.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 95% of the total text.

Page 1 of 2

Memory Cell With Minimized Negative Resistance Effects

A complementary transistor switch (CTS) memory cell has a layout which minimizes extrinsic resistance of the NPN base region by splitting the base contact between two P+ base diffusions coupled by a Schottky barrier diode contact. This minimization of the extrinsic base resistance decreases the negative dynamic resistance effects of the cell which is necessary for stable operation. The electrical circuit of the cell is shown in Fig. 1. The circuit includes first and second cross-coupled bipolar NPN transistors T1 and T2, respectively, each having a pair of dual emitters, first and second PNP transistors T3 and T4, respectively, and first and second Schottky barrier diodes D1 and D2, respectively. A cross-section of the layout of the half cell, i.e., devices T1, T3 and D1, is illustrated in Fig. 2. As seen in Fig. 2, the current path CP passes through only a very small segment of the base of transistor T1. The current flows from the word top electrode WT through the emitter, base and collector of PNP transistor T3, then into contact C1 and through Schottky barrier diode D1 to the N+ subcollector region and successively through the N-collector, P+ base and dual N+ emitters of transistor T1 to word bottom WB and bit line BL0 contacts. This layout avoids the flow of current along the horizontal direction or long dimension of the P+ base region of transistors T1 and T2 and, therefore, minimizes extrinsic base resi...