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Browse Prior Art Database

Formation of Sub-Micron Patterns With Negligible Tolerance

IP.com Disclosure Number: IPCOM000047349D
Original Publication Date: 1983-Nov-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 4 page(s) / 56K

Publishing Venue

IBM

Related People

Abbas, SA: AUTHOR [+2]

Abstract

In defining sub-micron features in silicon integrated circuit technology, one normally resorts to the use of electron beam resist exposure machines. However, these machines have certain drawbacks. Among these drawbacks is the large investment required and also the image tolerance which can be a sizable percentage of the nominal width and the throughput limitations. It has already been shown in, for example, U.S. Patent 4,322,883 that with self-aligned metal technology, sub-micron studs and spacings can be obtained with enhanced tolerance (about 10 to 20 nanometers) determined by thermal oxidation or chemical vapor deposition (CVD) tolerances. However, this does not solve the problem of image tolerance on dimensions defined by the studs. These spacings are still determined by the capability of the lithographic tool being used.

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Formation of Sub-Micron Patterns With Negligible Tolerance

In defining sub-micron features in silicon integrated circuit technology, one normally resorts to the use of electron beam resist exposure machines. However, these machines have certain drawbacks. Among these drawbacks is the large investment required and also the image tolerance which can be a sizable percentage of the nominal width and the throughput limitations. It has already been shown in, for example, U.S. Patent 4,322,883 that with self-aligned metal technology, sub-micron studs and spacings can be obtained with enhanced tolerance (about 10 to 20 nanometers) determined by thermal oxidation or chemical vapor deposition (CVD) tolerances. However, this does not solve the problem of image tolerance on dimensions defined by the studs. These spacings are still determined by the capability of the lithographic tool being used. An illustration of this is shown in Fig. 1 wherein the WX is the tolerance on the image.

The WX for an electron beam exposure is about 0.7 micron. Another approach can define structures and openings which are not only sub-micron in dimension but also with tolerances that are basically negligible, such as about 10 to 20 nanometers. This process can be implemented in two steps. First, form the studs 8 of 0.8 to 1.0 microns in width by thermal oxidation of a polysilicon layer protected by silicon nitride on the layer's top and bottom. Here, the availability of the high pressure oxidation process will enhance the flexibility of stud formation. Then, remove the silicon nitride and polysilicon to leave the free-standing stud 8, as seen in Fig. 2.

Second, one can go through another sequence of stud formation using the first set of studs 8 as structures to define the second set of studs. This is illustrated in Fig. 3, wherein newly formed studs 9 are shown. Fig. 4 shows the studs 9 after the removal of stud 10 by etching. Clearly, the spacing, X, between the studs can be made very small, and what is more, the tolerance, WX, on the spacing will be negligible. Bipolar devices and FET devices can be made by this process with excellent tolerances without the need for electron beam machines or even X-ray lithography. One can also extend this technique by using the sidewall instead of the stud as the building block and thus achieve sub-micron dimensions with negligible tolerances. A lateral bipolar device with controlled sub-micron-wide base width using the "double stud" concept can be formed by the following process. A lateral PNP device is formed by this process, but obviously one can interchange the doping species to obtain a lateral NPN device. After recessed oxide isolation (ROI) formation, we proceed as follows: 1. Implant through SiO2 layer 10 with phosphorous or arsenic ions to form the N region within the ROI. 2.

Deposit Si3N4 layer 12. 3. Deposit 1 to 1.2-micron layer 14 of polysilicon. 4. Deposit Si3N4 layer 16. 5. Define one base edge by lithography and...