Browse Prior Art Database

Bipolar Read-Only Memory With Three-State Cells

IP.com Disclosure Number: IPCOM000047353D
Original Publication Date: 1983-Nov-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 43K

Publishing Venue

IBM

Related People

Giuliani, SW: AUTHOR [+2]

Abstract

A conventional ROM (read-only memory) can be built with an array of diodes or transistors. A four-state ROM has been proposed where a high barrier Schottky diode, a low barrier Schottky diode, a P-N junction diode or the absence of any diode can be personalized at the intersection of the word and bit lines. This effectively doubles the array density. The proposed four-state ROM requires that the forward voltage difference between these devices can be accurately sensed to determine bit line state. The V-I curves for these diodes are essentially as shown in Fig. 1. These curves are sensitive to variations in process, temperature, current level, etc.

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Bipolar Read-Only Memory With Three-State Cells

A conventional ROM (read-only memory) can be built with an array of diodes or transistors. A four-state ROM has been proposed where a high barrier Schottky diode, a low barrier Schottky diode, a P-N junction diode or the absence of any diode can be personalized at the intersection of the word and bit lines. This effectively doubles the array density. The proposed four-state ROM requires that the forward voltage difference between these devices can be accurately sensed to determine bit line state. The V-I curves for these diodes are essentially as shown in Fig. 1. These curves are sensitive to variations in process, temperature, current level, etc., and extreme care is necessary in the sense amplifier circuit design to avoid errors due to the crossing of the high barrier SBD and P-N junction diode curves, as illustrated in Fig. 1. Disclosed is a technique which eliminates the use of the P-N junction diode in the array.

Now, each cell will have one of three possible states instead of four. The array density improvement will be 50% instead of 100%. As explained hereinafter, for conventional applications outputs will be converted into binary digits. In accordance with this disclosure (Fig. 2), two bit lines (t0, t1) are decoded to three data outputs (b0, b1, b2). (In a conventional ROM, each bit line is translated into a single data output which reflects the '1' or '0' state of the bit line.) Each horizontal bit line (F...