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Fault-Tolerant Paging Store

IP.com Disclosure Number: IPCOM000047354D
Original Publication Date: 1983-Nov-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 35K

Publishing Venue

IBM

Related People

Ryan, PM: AUTHOR

Abstract

By the addition of a controllably indexed, parallel load shift register to each column of chips in a paging store array, the bits of data obtained from each array access may be realigned and placed into respective output data words so that no more than a correctable number of faulty bits appear in any word. The basic structure of each memory card comprises an array of chips 1 arranged, for example, in 29 rows and 8 columns. Each chip, in this example, possesses 8K addresses and delivers 9 bits per access. Each array column of chips feeds a respective 9-bit, parallel input-serial output shift register 2. Each shift register is parallel-loaded with 9 bits from the addressed one of the chips in the column associated with the shift register during each array access.

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Fault-Tolerant Paging Store

By the addition of a controllably indexed, parallel load shift register to each column of chips in a paging store array, the bits of data obtained from each array access may be realigned and placed into respective output data words so that no more than a correctable number of faulty bits appear in any word. The basic structure of each memory card comprises an array of chips 1 arranged, for example, in 29 rows and 8 columns. Each chip, in this example, possesses 8K addresses and delivers 9 bits per access. Each array column of chips feeds a respective 9-bit, parallel input-serial output shift register 2. Each shift register is parallel-loaded with 9 bits from the addressed one of the chips in the column associated with the shift register during each array access. Successive chips in the same column provide 9 bits to the respective register in successive array accesses. Each register supplies one bit of each accessed word as the loaded registers are shifted out in unison. Permutation of the addresses for accessing the array chips permits the array chips of each column of chips to be accessed sequentially beginning with any desired starting point. During a given access using zero permutation, all column registers are loaded simultaneously with data from chips in the same array row. With other permutations, the registers can be loaded initially by chips in different array rows, depending upon the permuted starting address of the starting c...