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Syndromes for Error Location Mapping of Memory Arrays

IP.com Disclosure Number: IPCOM000047356D
Original Publication Date: 1983-Nov-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 45K

Publishing Venue

IBM

Related People

Aichelmann, FJ: AUTHOR

Abstract

Syndrome bits generated by ECC circuitry are stored, along with corresponding error word location data, to form an error map of a memory array. A saving of space is realized for storing the error map relative to the technique wherein error word location is stored together with the erroneous word. Moreover, the mapping of errors by the recording of syndrome bits can occur online while the customer is using the computer and without requiring that the system be diverted to a maintenance schedule for carrying out diagnostic programs. The syndrome is valid for pointing to the bits in error if the quantity of errors is less than or equal to the correction capability of the ECC code. Information read from memory consists of data bits (Di) and check bits (Cj).

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Syndromes for Error Location Mapping of Memory Arrays

Syndrome bits generated by ECC circuitry are stored, along with corresponding error word location data, to form an error map of a memory array. A saving of space is realized for storing the error map relative to the technique wherein error word location is stored together with the erroneous word. Moreover, the mapping of errors by the recording of syndrome bits can occur online while the customer is using the computer and without requiring that the system be diverted to a maintenance schedule for carrying out diagnostic programs. The syndrome is valid for pointing to the bits in error if the quantity of errors is less than or equal to the correction capability of the ECC code. Information read from memory consists of data bits (Di) and check bits (Cj). The data bits are processed by passing through the check bit generator 1 to produce a new set of check bits termed (Gj).

The new check bits (Gj) and those received from the memory (Cj) are compared (2) for a match or mismatch to determine the presence of error. This check bit comparision produces an output on line 3 termed syndrome (Sj) bits which classify (4) the output data condition and, in addition, through either table lookup or decode, produce the specific bit modification (5, 6) for error correction. The corrected data bits on line 7 are applied to generator 8 to produce corrected parity bits which are selectively applied via AND gate 9 and OR gate 10 to...