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Block-Controlled Address Permutation Logic for Fault Dispersion

IP.com Disclosure Number: IPCOM000047357D
Original Publication Date: 1983-Nov-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 32K

Publishing Venue

IBM

Related People

Singh, S: AUTHOR [+2]

Abstract

An adder is used to add a constant to a memory address, thereby changing the address as if it were incremented in an address counter the number of times equal to the constant. The new address is then exclusive-ORed with another binary vector bit by bit to produce a 2n(2n-1) address permutations where n = the number of bits in the counter and in the binary vector. The permuted addresses are used to disperse faulty memory bits among different ECC words so that the number of faulty bits in any fetched ECC word does not exceed the available bit correction capability. The permutation logic is such that it is simple and yet can work on a large block (number of memory words). The circuit schematic is shown in the figure.

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Block-Controlled Address Permutation Logic for Fault Dispersion

An adder is used to add a constant to a memory address, thereby changing the address as if it were incremented in an address counter the number of times equal to the constant. The new address is then exclusive-ORed with another binary vector bit by bit to produce a 2n(2n-1) address permutations where n = the number of bits in the counter and in the binary vector. The permuted addresses are used to disperse faulty memory bits among different ECC words so that the number of faulty bits in any fetched ECC word does not exceed the available bit correction capability. The permutation logic is such that it is simple and yet can work on a large block (number of memory words). The circuit schematic is shown in the figure. There are two major components of the permutation logic 1:
(1) A binary adder (ALU2) and (2) shift register (or simple latches) and 8 EXOR gates. Since such permutation logic is required for each memory section, which forms the total memory system, the permutation logic should be able to disperse errors in large blocks of memory. An 8-bit arithmetic logical unit (ALU) is available on a chip, and the shift register only requires 8 latches. Therefore, such permutation logic can be realized within two standard dip modules and can provide a block of 256 (512) (including the use of carry out of ALU) words in which addresses can be permuted to disperse the errors. If the memory is organized in do...