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Fault Realignment Through Grouping of Compatible Faulty Memory Chips

IP.com Disclosure Number: IPCOM000047358D
Original Publication Date: 1983-Nov-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Ryan, PM: AUTHOR

Abstract

Fault tolerance in memories is enhanced by mapping and categorizing faulty memory chips by fault type and then permitting only those chips having compatible faults to contribute bits to the same error-correcting code (ECC) words. One method of fault tolerance in memories is to move (electronically rather than physically) faulty chips so that they do not simultaneously supply data to any one ECC word. Another method is to steer the data from faulty chips so that most of the chips supply ECC words in some small block of addresses and then, by software means, assure that no reference is made to the affected block (address block de-allocation).

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Fault Realignment Through Grouping of Compatible Faulty Memory Chips

Fault tolerance in memories is enhanced by mapping and categorizing faulty memory chips by fault type and then permitting only those chips having compatible faults to contribute bits to the same error-correcting code (ECC) words. One method of fault tolerance in memories is to move (electronically rather than physically) faulty chips so that they do not simultaneously supply data to any one ECC word. Another method is to steer the data from faulty chips so that most of the chips supply ECC words in some small block of addresses and then, by software means, assure that no reference is made to the affected block (address block de-allocation). A combination of the two techniques provides improved ability to tolerate faults relative to the first method alone, while also avoiding the de-allocation of memory required by the second method. This improved approach is based on the chip testing and categorizing of the chip- failure mechanisms that produce uncorrectable errors. A 64-kilobit chip is typically organized as 256 wordlines by 256 bit lines. Faults can disable one or a few single cells, one or a few word lines, one or a few bit lines, or an entire chip. Typically, chip-killing faults are less frequent than other types of faults. Large memories are usually organized such that no array chip supplies more than one bit to any single ECC word. The chips which together supply all the bits in a block of ECC words are identified as a "segment" of memory....