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Distributed Permutation Logic for Fault-Tolerant Memories

IP.com Disclosure Number: IPCOM000047359D
Original Publication Date: 1983-Nov-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Related People

Singh, S: AUTHOR [+2]

Abstract

Address permutation logic facilitates the dispersion of faulty bits throughout a memory in such a way that the number of faults per data word is brought within the error correction capability of the system. It has been found, however, that when the faulty bit dispersion logic itself is distributed throughout the memory system, a few bits of permutation logic at each system level (e.g., chip, module, card and board) provide wider fault coverage than do a large number of bits of centralized permutation logic at one location only (e.g., card). As shown in the figure, address bits arriving at the permutation logic on bus 1 are branched to card bus 2, module bus 3 and chip bus 4. Each of the branched addresses is selectively incremented in a respective adder such as address 5, 6 and 7.

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Distributed Permutation Logic for Fault-Tolerant Memories

Address permutation logic facilitates the dispersion of faulty bits throughout a memory in such a way that the number of faults per data word is brought within the error correction capability of the system. It has been found, however, that when the faulty bit dispersion logic itself is distributed throughout the memory system, a few bits of permutation logic at each system level (e.g., chip, module, card and board) provide wider fault coverage than do a large number of bits of centralized permutation logic at one location only (e.g., card). As shown in the figure, address bits arriving at the permutation logic on bus 1 are branched to card bus 2, module bus 3 and chip bus 4. Each of the branched addresses is selectively incremented in a respective adder such as address 5, 6 and 7. In the event that fault detection circuitry (not shown) has determined the presence of an intra chip type of fault, the adder 6 at the module 1 level will permute the chip addresses on bus 3 in accordance with the offset signal from permutation vector (PV) generator 8 which is triggered by a signal on shift bus 9 from the fault detection circuitry. The permuted address substitutes a good chip for the detected faulty one when a data word is written or read from memory, thereby avoiding an uncorrectable number of faulty bits in the data word. The data word comprises a train of bits, each of which is assigned to a respective selecte...