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Wafer Map Organization for Counterbalancing Auto-Doping Effects in Semiconductor Processing

IP.com Disclosure Number: IPCOM000047362D
Original Publication Date: 1983-Nov-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Mollier, P: AUTHOR [+2]

Abstract

The proposal relates to an arrangement of the chips on a wafer during the manufacturing process to reduce the percentage of subcollector area to a value compatible with the process requirement to counterbalance auto-doping effects. Some processing steps in semiconductor manufacturing are influenced by the amount of impurities contained in the wafers. This auto-doping effect is particularly noticeable when hot process steps involving light doping doses are applied to materials containing highly doped areas. That is the case for silicon epitaxial growth on wafers containing exposed areas of highly doped subcollector beds and isolation walls.

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Wafer Map Organization for Counterbalancing Auto-Doping Effects in Semiconductor Processing

The proposal relates to an arrangement of the chips on a wafer during the manufacturing process to reduce the percentage of subcollector area to a value compatible with the process requirement to counterbalance auto-doping effects. Some processing steps in semiconductor manufacturing are influenced by the amount of impurities contained in the wafers. This auto-doping effect is particularly noticeable when hot process steps involving light doping doses are applied to materials containing highly doped areas. That is the case for silicon epitaxial growth on wafers containing exposed areas of highly doped subcollector beds and isolation walls. For example, for the regular NPN planar transistor on a P-substrate (N+ arsenic subcollector, P+ boron isolation, N-epitaxy) the larger the subcollector area, the higher the epitaxial layer doping, if no compensation is applied during the processing. This effect not only changes the average doping of the involved layer (i.e., epitaxy) but also alters its profile since the effect varies during the processing time. To prevent this auto-doping effect from affecting the manufactured chip, the dopant concentration in the gas flow is adjusted according to the N+/P+ areas of the wafer to compensate the average effect of the auto-doping, and the profile change is taken into account when generating the electrical model of the device. In some case...