Browse Prior Art Database

A/D Logic Without Counter

IP.com Disclosure Number: IPCOM000047365D
Original Publication Date: 1983-Nov-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Related People

Cukier, M: AUTHOR [+3]

Abstract

Represented in Fig. 1 is a conventional analog-to-digital (A/D) converter. At the beginning of the conversion, voltage V is stable. The "START OF CONV." signal clears counter Co and the Ro to Rn registers. Through the DECODE block (combinational logic) all registers Ro...Rn are reset (all 0) at this time, Co = 0. Then, a clock occurs, and Co is incremented. Ro (latch corresponding to sign) is conditionally set if the comparator (COMP) output is negative. Next, latch R1 corresponding to the MSB is unconditionally set, Co = 1. At the next clock occurrence, Co = 2. R1 is conditionally reset if the comparator output is negative. R2 is unconditionally set. When Co = x, latch R(x-1) is conditionally reset if the comparator output is negative, while Rx is unconditionally set. When Co = n, the signal "END OF CONV." is activated.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 71% of the total text.

Page 1 of 2

A/D Logic Without Counter

Represented in Fig. 1 is a conventional analog-to-digital (A/D) converter. At the beginning of the conversion, voltage V is stable. The "START OF CONV." signal clears counter Co and the Ro to Rn registers. Through the DECODE block (combinational logic) all registers Ro...Rn are reset (all 0) at this time, Co = 0. Then, a clock occurs, and Co is incremented. Ro (latch corresponding to sign) is conditionally set if the comparator (COMP) output is negative. Next, latch R1 corresponding to the MSB is unconditionally set, Co = 1. At the next clock occurrence, Co = 2. R1 is conditionally reset if the comparator output is negative. R2 is unconditionally set. When Co = x, latch R(x-1) is conditionally reset if the comparator output is negative, while Rx is unconditionally set. When Co = n, the signal "END OF CONV." is activated. The following table details equation of successive approximative register for a step conversion.

(Image Omitted)

Latch R4 is not required in the classical A/D approach. Equations (I) SET Ro = (COUNT = 0). COMP SET R1 = (COUNT = 0) + (COUNT = 1). COMP

SET R2 = (COUNT = 1) + (COUNT = 2). COMP

SET R3 = (COUNT = 2) + (COUNT = 3). COMP

SET R4 = (COUNT = 3) RESET Ro = START CONV. + (COUNT = 0). COMP RESET R1 = START CONV. + (COUNT = 1) COMP RESET R2 = START CONV. + (COUNT = 2) COMP

RESET R3 = START CONV. + (COUNT = 3) COMP

RESET R4 = START CONV. Compact A/D logic: In the equations (I), the following properties can be checked:...