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Error Checking Mechanism for the Input to and Operation of a Decoder

IP.com Disclosure Number: IPCOM000047388D
Original Publication Date: 1983-Nov-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 25K

Publishing Venue

IBM

Related People

Celeste, JJ: AUTHOR [+2]

Abstract

It is possible to provide an effective check of the input to and the operation of a decoder which decodes a multi-bit input plus parity into a one out of many outputs without the use of a tree structure parity check mechanism, by grouping the outputs into those which correspond to an input parity of one significance and those which correspond to an input parity of the other significance, ORing the output signals of each group and comparing the two signals generated with the input parity. Error will be signalled if the input parity is incorrect or if the decoder generates an output signal in both groups or in the incorrect parity group. The mechanism will not detect incorrect decoding or multiple decoding in the correct group, nor will it detect cancelling errors in the input to and the operation of the decoder.

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Error Checking Mechanism for the Input to and Operation of a Decoder

It is possible to provide an effective check of the input to and the operation of a decoder which decodes a multi-bit input plus parity into a one out of many outputs without the use of a tree structure parity check mechanism, by grouping the outputs into those which correspond to an input parity of one significance and those which correspond to an input parity of the other significance, ORing the output signals of each group and comparing the two signals generated with the input parity. Error will be signalled if the input parity is incorrect or if the decoder generates an output signal in both groups or in the incorrect parity group. The mechanism will not detect incorrect decoding or multiple decoding in the correct group, nor will it detect cancelling errors in the input to and the operation of the decoder. The figure shows a command register 1 connected to receive a multi-bit command field latched into the command section 2 of the register and a corresponding parity bit latched into a parity latch 3 forming part of the register. The command section of the register is connected by parallel paths 4 to a command decoder 5 having two groups of output lines, one group 6 corresponding to decoded command fields for which the parity bit should be "1" and the other group 7 corresponding to command fields for which the corresponding parity bit should be "0". The decoder, when operating correctly, sho...