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High-Speed One-Bit Cipher Feedback Arrangement

IP.com Disclosure Number: IPCOM000047390D
Original Publication Date: 1983-Nov-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 3 page(s) / 43K

Publishing Venue

IBM

Related People

Smith, JL: AUTHOR

Abstract

This article discloses a one-bit cipher feedback (CFB) arrangement which attains high-speed operation by using the multiplicity of cipher engines operating in parallel. Fig. 1 illustrates the CFB mode of operation for a transmitting and receiving station connected via a communication line. The operation is essentially a stream method of encryption in which the algorithm, e.g., the Data Encryption Standard (DES), is operated under control of the cipher key K to generate n pseudo-random bits, where 1 < n < 64, which are Exclusive-ORed with n bits of plaintext to form n bits of ciphertext.

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High-Speed One-Bit Cipher Feedback Arrangement

This article discloses a one-bit cipher feedback (CFB) arrangement which attains high-speed operation by using the multiplicity of cipher engines operating in parallel. Fig. 1 illustrates the CFB mode of operation for a transmitting and receiving station connected via a communication line. The operation is essentially a stream method of encryption in which the algorithm, e.g., the Data Encryption Standard (DES), is operated under control of the cipher key K to generate n pseudo-random bits, where 1 < n < 64, which are Exclusive-ORed with n bits of plaintext to form n bits of ciphertext. The n bits of ciphertext are fed back to the input of the algorithm by shifting the current input n bits to the left and appending the n bits of ciphertext to the right of the shifted input to produce a new input to the algorithm for the next cycle of operation. The n bits of ciphertext are also transmitted via the communication line to the input of the algorithm at the receiving station. The n bits of ciphertext received at the receiving station are fed to the input of the algorithm by shifting the current input n bits to the left and appending the n bits of ciphertext to the right of the shifted input to produce a new input to the algorithm for the next cycle of the algorithm at the receiving station. The algorithm at the receiving station is operated under control of the cipher key K to generate the same n pseudo-random bits which are Exclusive- ORed with the n bits of ciphertext received from the transmitting station to form n bits of plaintext. This process of encryption and decryption continues until the entire message has been decrypted at the receiving station. Synchronization of the two stations is normally accomplished by the transmission of a synchronizing message at the beginning of each data transfer. This message is generated at the transmitting station by cycling a seed value through the algorithm at the transmitting station and using the resulting output as the synchronizing message to be sent to the receiving station. The synchronizing message, which is identical at both the transmitting and receiving stations, is used as the initial input to the algorithm at both the transmitting and receiving stations in order to generate the cryptographic bit-stream. As the value of n approaches the value of 1, the limitation on the speed of operation becomes excessive, especially in loop applications. Accordingly, the present disclosure provides a modification of the data encryption device at the transmitting and receiving stations as to permit higher speed operation for use in full duplex systems, point to point or loop applications. The technique to reduce unit delay is to forego use of the synchronizing message and the extensive buffering and delays therefor. This is acceptable in a full duplex environment, as synchronism is established when each cipher engine at a receiving station has obtained...