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Multitasking Microprocessor Level Instructions

IP.com Disclosure Number: IPCOM000047418D
Original Publication Date: 1983-Nov-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Korte, LA: AUTHOR

Abstract

The microprocessor interval timer is arranged to produce an interruption signal at fixed intervals. At the branch-to location in processor memory, an interruption program saves the registers and the entire program counter stack contents of the interrupted program. The program fetches the registers and the entire stack contents for a second program and loads this information into the current registers and program counter stack space. Control is then returned to the second program at the new address specified in the altered current stack. The modified register space is used in the program execution. At the next interval timer interruption, control is transferred to the original program precisely at its termination point. Two or more programs can be executed in this time-shared manner.

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Multitasking Microprocessor Level Instructions

The microprocessor interval timer is arranged to produce an interruption signal at fixed intervals. At the branch-to location in processor memory, an interruption program saves the registers and the entire program counter stack contents of the interrupted program.

The program fetches the registers and the entire stack contents for a second program and loads this information into the current registers and program counter stack space. Control is then returned to the second program at the new address specified in the altered current stack. The modified register space is used in the program execution.

At the next interval timer interruption, control is transferred to the original program precisely at its termination point. Two or more programs can be executed in this time-shared manner. The first and second programs and the interruption program are written in microprocessor level instructions. Background A typical microprocessor has an interruption system that permits the processor to branch from its current program to a program that handles the interruption. For example, the processor may include a timer that produces an interruption signal after a predetermined interval. In response to a timer interruption, the program counter is reset to execute the next instruction from a predetermined location in processor memory. The processor also has means for the current program to call another program. When the processor branch...