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High Performance, Single Bit Error Correction

IP.com Disclosure Number: IPCOM000047462D
Original Publication Date: 1983-Nov-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 68K

Publishing Venue

IBM

Related People

Anand, HS: AUTHOR

Abstract

A system is shown in Fig. 1 for correcting data stored in a control store 10 where the error is limited to one failing bit per address. The system includes Data In logic block 11 and Data Out logic block 12 for writing an 18-bit word to store 10 and reading an 18-bit word from store 10, respectively. A 12-bit address is supplied to store 10 on line 14 through OR-gate 15 which has a second input terminal from a temporary address register 16. The output of register 16 is also connected to failing address trap registers 17. Registers 17 are connected to address comparison and flag logic block 18 which controls the Data Out logic and the parity check and trap logic block 20. The operation of the storage system of Fig. 1 is as follows.

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High Performance, Single Bit Error Correction

A system is shown in Fig. 1 for correcting data stored in a control store 10 where the error is limited to one failing bit per address. The system includes Data In logic block 11 and Data Out logic block 12 for writing an 18-bit word to store 10 and reading an 18-bit word from store 10, respectively. A 12-bit address is supplied to store 10 on line 14 through OR-gate 15 which has a second input terminal from a temporary address register 16. The output of register 16 is also connected to failing address trap registers 17. Registers 17 are connected to address comparison and flag logic block 18 which controls the Data Out logic and the parity check and trap logic block 20. The operation of the storage system of Fig. 1 is as follows. A 12-bit address is supplied to the control store (CS) 10, along with an 18-bit word through Data In block 11. The address is trapped in register 16. The newly stored data is next read out and parity checked in block
20. If parity is OK, then a read or write operation for another word follows. If parity indicates an error, the word is rewritten back into memory in complementary form, and the address from register 16 is trapped in a failing address trap register 17 and a flag is set for that address. For a read operation, if the address stored in the trap register 17 and the new address are equal and a flag is set for the address location, then the data is inverted when it is read out.

If, on...