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Browse Prior Art Database

Dielectrically Isolated CMOS Structure Fabricated by Reverse Trench Process

IP.com Disclosure Number: IPCOM000047488D
Original Publication Date: 1983-Nov-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 3 page(s) / 43K

Publishing Venue

IBM

Related People

Lai, FSJ: AUTHOR

Abstract

This article relates generally to processes for fabricating electrically isolated semiconductor devices and more particularly to a process for fabricating electrically isolated complementary metal-oxide-semiconductor (CMOS) devices to solve the latch-up problem in ==/== devices. (Image Omitted) The latch-up problem in CMOS structures is primarily caused by the depletion region of the n-well or p-well. If the whole well can be surrounded by dielectric materials, the CMOS structure becomes latch-up free. This article shows a process whereby a dielectrically isolated CMOS structure is fabricated using a "reverse trench" process. The process includes the following steps: 1. Referring to Fig.

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Dielectrically Isolated CMOS Structure Fabricated by Reverse Trench Process

This article relates generally to processes for fabricating electrically isolated semiconductor devices and more particularly to a process for fabricating electrically isolated complementary metal-oxide-semiconductor (CMOS) devices to solve the latch-up problem in ==/== devices.

(Image Omitted)

The latch-up problem in CMOS structures is primarily caused by the depletion region of the n-well or p-well. If the whole well can be surrounded by dielectric materials, the CMOS structure becomes latch-up free. This article shows a process whereby a dielectrically isolated CMOS structure is fabricated using a "reverse trench" process. The process includes the following steps: 1. Referring to Fig. 1, a sandwich stack of a

polysilicon layer between layers of silicon

dioxide is formed on top of a p-type silicon

substrate. In this structure, the polysilicon

layer is used as a nucleator for a following

epitaxial growth step. It can be very thin. 2. Using reactive ion etching (RIE), the stack

and p-type silicon substrate of Fig. 1 are etched,

as shown in Fig. 2, forming a trench. 3. As shown in Fig. 3, a layer of chemical vapor

deposited (CVD) oxide is deposited on the wafer forming

on the bottom and sidewalls of the trench of Fig. 2. The

thickness can be controlled to obtain the desired

isolation. 4. Using RIE, the CVD oxide is etched away,

leaving the sidewall oxide as well as the

insulator. Nitrogen is then implanted into the

exposed silicon, forming the structure of Fig. 4. 5. As shown in Fig. 5, n-type silicon...