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New Functional Block Applied to Computer Organization

IP.com Disclosure Number: IPCOM000047499D
Original Publication Date: 1983-Nov-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 3 page(s) / 79K

Publishing Venue

IBM

Related People

Dill, FH: AUTHOR [+4]

Abstract

VLSI has provided designers with many functional chips which can be fashioned into many configurations. However, such functional chips tend to be either microprocessors of various kinds or very specialized functions, such as floating point multipliers, etc. More specifically, the trend is to build on-chip processors and to include memory (random-access and/or read-only) whenever necessary and if possible. The focus tends to be on traditional processing but done on-chip. This eventually leads to problems with interfacing to a large memory. Since memory is ultimately the key element in system organization and performance, a design is described herein which first starts with a memory chip and then logical functions are added to achieve a versatile processor building block.

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New Functional Block Applied to Computer Organization

VLSI has provided designers with many functional chips which can be fashioned into many configurations. However, such functional chips tend to be either microprocessors of various kinds or very specialized functions, such as floating point multipliers, etc. More specifically, the trend is to build on-chip processors and to include memory (random-access and/or read-only) whenever necessary and if possible. The focus tends to be on traditional processing but done on-chip. This eventually leads to problems with interfacing to a large memory. Since memory is ultimately the key element in system organization and performance, a design is described herein which first starts with a memory chip and then logical functions are added to achieve a versatile processor building block. A schematic illustration of the use of the functional building block memory chip in one organization is shown in Fig. 1. Part or all of the arithmetic/logic unit (ALU) functions are distributed across the memory chips in a bit-sliced manner (one or more bits per chip). The size of the general purpose register file can be reduced to one or a few registers needed to hold the first operand. The remainder of the register file is replaced by the memory. Any memory location can be the second operand, greatly increasing the power of the system. The first operand from data register 1 is sent to the memory chips simultaneously with the access of the second operand from memory. The ALU function is performed at the output of the sense amplifiers of the memory, and the result is stored back into the second operand location in memory. In Fig. 2, the enhanced memory chip is shown in greater detail. The data path width to each chip is one bit, and the on-chip arithmetic/logic unit is designated by LU. The LU performs any of the 16 Boolean operations which are possible on two one-bit operands: such as A, B, A, B, A AND B, A OR B, A XOR B, etc. The particular operation is declared by an external source or control field. For a dynamic RAM (random-access memory) the LU operation becomes part of the normal read-regenerate-write cycle. For the bit selected by the bit decoder, this cycle becomes read- regenerate-operate-write, whereas for all other bits in the (example) 256-bit word the LU operation does not occur; they are simply refreshed. For a static RAM the regenerate operation is unnecessary, and a read-before-write operation may have to be added. The latch in Fig. 2 holds the data from the read cycle as output while the LU result...