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Cache Coherency Without Line Exclusivity in MP Systems Having Store-In Caches

IP.com Disclosure Number: IPCOM000047502D
Original Publication Date: 1983-Nov-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Pomerene, JH: AUTHOR [+4]

Abstract

By modifying the function of the storage control unit (SCU), a multiprocessor (MP) system having store-in caches is enabled to operate with the same versatility as an MP system having store-through caches, thereby eliminating the requirement for line exclusivity and greatly reducing the occurrence of cross-interrogates. In presently available MP systems having store-in cache organizations, such as the IBM 3081 system, for example, the need for cache coherency requires those lines which are targets of a processor's storage requests (stores) to be held within that processor's cache exclusive of other caches in the system, and such stores must be held off until the targeted lines have been invalidated in all other caches.

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Cache Coherency Without Line Exclusivity in MP Systems Having Store-In Caches

By modifying the function of the storage control unit (SCU), a multiprocessor (MP) system having store-in caches is enabled to operate with the same versatility as an MP system having store-through caches, thereby eliminating the requirement for line exclusivity and greatly reducing the occurrence of cross- interrogates. In presently available MP systems having store-in cache organizations, such as the IBM 3081 system, for example, the need for cache coherency requires those lines which are targets of a processor's storage requests (stores) to be held within that processor's cache exclusive of other caches in the system, and such stores must be held off until the targeted lines have been invalidated in all other caches. This line exclusivity requirement leads to cross-interrogates between processors at an undesirably high frequency and degrades the performance of the MP system. The troublesome line exclusivity requirement can be eliminated from MP systems having store-in caches if the SCU function is enhanced to provide the same capabilities as those possessed by store-through machines. In the modified storage control procedure, when a processor broadcasts the first store to a given line, the SCU establishes a primacy for that line in behalf of that processor. Subsequent stores need not be sent to the SCU. At some later time, the SCU will invalidate the targeted line in the caches of ot...