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Split Second-Level Cache

IP.com Disclosure Number: IPCOM000047503D
Original Publication Date: 1983-Nov-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Related People

Pomerene, JH: AUTHOR [+4]

Abstract

This level-splitting technique enables a new level to be created i memory hierarchy without requiring that it be significantly larger than the next higher level. In current multilevel memory hierarchies, each level is a subset of the next lower level, thereby requiring that the lower level be significantly larger. Such an approach can limit the number of levels. For instance, in a memory hierarchy having three cache levels L1, L2 and L3, wherein L1 stores 64K bits and L2 stores 1M bits, if L2 is required to be a subset of L3, then L3 would require a 2M bit capacity to justify itself. In many cases, this large cache size would be prohibitive. A different approach, therefore, is needed in the design of L2 and L3.

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Split Second-Level Cache

This level-splitting technique enables a new level to be created i memory hierarchy without requiring that it be significantly larger than the next higher level. In current multilevel memory hierarchies, each level is a subset of the next lower level, thereby requiring that the lower level be significantly larger. Such an approach can limit the number of levels. For instance, in a memory hierarchy having three cache levels L1, L2 and L3, wherein L1 stores 64K bits and L2 stores 1M bits, if L2 is required to be a subset of L3, then L3 would require a 2M bit capacity to justify itself. In many cases, this large cache size would be prohibitive. A different approach, therefore, is needed in the design of L2 and L3. The same performance can be achieved with an L3 of only 1M bit capacity if the contents of L3 are disjoint from those of L2 and L3 is treated as an adjunct of L2. In effect, the logical L2 is split across two physical levels each containing a subset of 1M bits. The directory and physical management of the split L2 is described below with reference to Figs. 1 and 2. The L2 directory can address lines in both the L2 and L3 cache levels. The MRU-LRU stack (Fig. 1) indicates which level contains the physical line and the position of that line in the most- recently-used/ least-recently-used order across the two levels. An access to the lower half of the congruence class will be an access to L3 and is treated as a physical miss from L2,...