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Firmware With Error Correction Code for Logic/Array Testing

IP.com Disclosure Number: IPCOM000047517D
Original Publication Date: 1983-Nov-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 3 page(s) / 55K

Publishing Venue

IBM

Related People

del Sol, PD: AUTHOR [+3]

Abstract

Firmware with Error Correction Code (ECC) capabilities enhances Functional Replacement Unit (FRU) failure detection and provides preventive maintenance to ensure data integrity. As shown in Fig. 1, a representative processor based on the IBM Series/1 product line may include a 22-bit wide storage bus 1 (16 data bits, 6 check bits) which, by way of ECC funnel 2 to ECC logic 3, Main Storage Data Register (MSDR) 4 and ECC bits register 5, comprises most of the data flow for storage operations. The ECC Logic performs check bit generation on writes, as well as syndrome bit generation on reads which are used to then locate and correct single-bit errors. A Single Error Correction-Double Error Detection (SEC-DED) code is implemented that has single-bit error correcting capability, as well as multiple-bit error detection.

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Firmware With Error Correction Code for Logic/Array Testing

Firmware with Error Correction Code (ECC) capabilities enhances Functional Replacement Unit (FRU) failure detection and provides preventive maintenance to ensure data integrity. As shown in Fig. 1, a representative processor based on the IBM Series/1 product line may include a 22-bit wide storage bus 1 (16 data bits, 6 check bits) which, by way of ECC funnel 2 to ECC logic 3, Main Storage Data Register (MSDR) 4 and ECC bits register 5, comprises most of the data flow for storage operations. The ECC Logic performs check bit generation on writes, as well as syndrome bit generation on reads which are used to then locate and correct single-bit errors. A Single Error Correction-Double Error Detection (SEC-DED) code is implemented that has single-bit error correcting capability, as well as multiple-bit error detection. In addition, however, firmware allows certain diagnose instructions to control the data flow through the ECC circuitry, thereby providing extensive data flow and array fault test capability. Specific ECC control modes are defined which are alterable by the microcode: CNTL BIT 0 CNTL BIT 1 MODE 0 0 Normal Mode

0 1 Report All Errors

1 0 Disable ECC Chk

1 1 Disable ECC Gen In the data flow diagram of Fig. 1, PATH 1 describes the 'Data' path on both Reads and Writes, regardless of ECC mode. On Reads with 'Disable ECC Chk mode on, however, the degate control is set to inhibit the error correct circuitry from modifying the data onto the MSDR. Path 2 is used to latch up the Main Storage Check Bits directly when trying to read an entire 22-bit word from Main Storage under the 'Disable ECC Chk' mode. For Reads in any other mode, Path 1 will be used to clock the resulting syndrome bits. Path 3 is used to latch the desired check bits on Writes under 'Disable ECC Gen' mode. On Writes in any other mode, the generated check bits will be clocked into the ECC Bits Register through Path 1. MODE 0: In normal mode the ECC logic is functional. Fig. 2 shows the logic used to

report storage errors. Single-bit

errors are reported as 'ECC Storage Check' in the

Processor Status Word (PSW) by way of blocks 6-8

in Fig. 2. Path 1 in Fig. 1 is used in this mode

for both Reads and Writes. MODE 1: In this mode single- as well as multiple-bit errors are reported in the PSW.

The microcode resets the machine back to

Mode 0 once it fields the error so

that any possible subsequent single-bit

(correctable) error will not cause the microcode

to loop. Path 1 is still used for both Reads and

Writes. Note that when 'Report All Errors') (MODE

1) is on (Fig. 2), all single-bit errors will be

1

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reported in the PSW. MODE 2: In this mode no ECC errors are reported. The data correcting circuitry is degated

as Main Storage Data is effectively

flushed through...