Browse Prior Art Database

Computer I/O With Single Phase Strobing

IP.com Disclosure Number: IPCOM000047518D
Original Publication Date: 1983-Nov-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 3 page(s) / 39K

Publishing Venue

IBM

Related People

Kimberly, DW: AUTHOR [+3]

Abstract

This I/O strobing technique can be used relative to the "integrated Digital Input/Output Non-Isolated Attachment" feature of the IBM Series/1 processor (reference sales literature publication GA34-0031-1, "IBM Series/1 Attachment Features Description") for simplifying and reducing the software associated with the direct control of the attachment feature. With the present "single phase" technique, a strobing signal presented to the device at the attachment feature interface --which ordinarily must undergo two phase reversals for each discrete data byte transfer between the attachment feature and the device (an "on" reversal and an "off" reversal) -- is manipulated under direct control of the Series/1 software to undergo only a single phase reversal per transfer.

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Computer I/O With Single Phase Strobing

This I/O strobing technique can be used relative to the "integrated Digital Input/Output Non-Isolated Attachment" feature of the IBM Series/1 processor (reference sales literature publication GA34-0031-1, "IBM Series/1 Attachment Features Description") for simplifying and reducing the software associated with the direct control of the attachment feature. With the present "single phase" technique, a strobing signal presented to the device at the attachment feature interface --which ordinarily must undergo two phase reversals for each discrete data byte transfer between the attachment feature and the device (an "on" reversal and an "off" reversal) -- is manipulated under direct control of the Series/1 software to undergo only a single phase reversal per transfer. The addressed device -- with special hardware or "micro-firmware" adaptation described below -- and the Series/1 attachment control software continually memorize the "last" state of the interface strobe (up or down), preceding any transfer, and to invoke a transfer the Series/1 causes the strobe to be reversed in state and the device reacts to each reversal to send or receive a byte of data (as instructed by the bit state on a separate Read/Write line). A hardware embodiment of such device adaptation is shown in the figure. Upon detecting the address of its device the output pin of decoder 1 becomes active (low). Concurrently, the strobe bit 2 reverses in state as described above. The reversal transition is low-pass filtered at 3 (to eliminate noise glitches), and inverted at 4 to provide true and complement phases of the strobe line condition as clocking inputs to "D" flip-flops 5 and 6. Gating inputs to these flip-flops are wired to a constant logical "1" voltage so that positive slope transitions of the strobe signal cause the output of flip-flop 5 to become active (high) and negative slope transitions activate flip-flop 6. When...