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Self-Aligned NPN Transistor Process

IP.com Disclosure Number: IPCOM000047523D
Original Publication Date: 1983-Dec-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 54K

Publishing Venue

IBM

Related People

Bergeron, DL: AUTHOR [+2]

Abstract

A process is provided for the formation of a self-aligned NPN transistor compatible with a shallow junction and a highly doped extrinsic base. The process uses ion implantation and lift-off techniques rather than polysilicon for self-alignment. Additionally, a Schottky barrier diode with a self-aligned guard ring may be fabricated simultaneously. As indicated in Fig. 1, the process includes growing a layer of silicon dioxide 10 on a semiconductor substrate 12 and then depositing a thin layer 14 of silicon nitride on layer 10. A first layer 16 of photoresist is applied over silicon nitride layer 14, and an opening 18 is formed therein for defining the emitter of the NPN transistor. As shown in Fig. 1, the opening 18 is made wider at the bottom than at the top of layer 16 by any known method.

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Self-Aligned NPN Transistor Process

A process is provided for the formation of a self-aligned NPN transistor compatible with a shallow junction and a highly doped extrinsic base. The process uses ion implantation and lift-off techniques rather than polysilicon for self-alignment. Additionally, a Schottky barrier diode with a self-aligned guard ring may be fabricated simultaneously. As indicated in Fig. 1, the process includes growing a layer of silicon dioxide 10 on a semiconductor substrate 12 and then depositing a thin layer 14 of silicon nitride on layer 10. A first layer 16 of photoresist is applied over silicon nitride layer 14, and an opening 18 is formed therein for defining the emitter of the NPN transistor. As shown in Fig. 1, the opening 18 is made wider at the bottom than at the top of layer 16 by any known method. By using reactive ion etching techniques, an opening 20 is made in silicon nitride layer 14 and silicon dioxide layer 10, with the thickness of photoresist layer 16 being reduced, as indicated in Fig. 2 at 16'. An aluminum masking layer 22 is evaporated over photoresist layer 16' and on substrate 12 through opening 20, forming an aluminum masking segment 22'. By using any suitable solvent, the photoresist layer 16' and the aluminum overlying layer 22 are removed. A second layer 24 of photoresist is applied over silicon nitride layer 14 and an opening 26 is formed therein for defining an extrinsic base of the NPN transistor. The remaining photoresist is hardened and baked and boron is implanted through silicon nitride and silicon dioxide layers 14 and 10, respectively, to form a P+ extrinsic base 28 in substrate 12, as illustrated in Fig.
3. The aluminum segment 22' and the photoresist layer 24 are stripped by using any known solvents and a thin screen layer 30 of silicon dioxide is grown on the exposed surface of substrate 12 within P+ e...