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Low Input Capacitance Sense Amplifier

IP.com Disclosure Number: IPCOM000047534D
Original Publication Date: 1983-Dec-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Towler, FJ: AUTHOR

Abstract

A latch-type sense amplifier is self-decoupling from bit/sense lines to provide lower input capacitance without the use of control pulses. A differential charge gain is also provided prior to setting the amplifier latch, and voltage drop on the high voltage side of the latch is minimized. In known latch-type sense amplifiers an isolation transistor is provided between an input node of the latch and the bit/sense line. A control pulse of given magnitude turns on the isolation transistor when a signal is being developed on the bit/sense line. The magnitude of the control pulse is then lowered to an intermediate voltage when the latch is set. Current will then flow through the isolation transistor into the low voltage side of the latch, discharging the line connected to the low voltage side.

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Low Input Capacitance Sense Amplifier

A latch-type sense amplifier is self-decoupling from bit/sense lines to provide lower input capacitance without the use of control pulses. A differential charge gain is also provided prior to setting the amplifier latch, and voltage drop on the high voltage side of the latch is minimized. In known latch-type sense amplifiers an isolation transistor is provided between an input node of the latch and the bit/sense line. A control pulse of given magnitude turns on the isolation transistor when a signal is being developed on the bit/sense line. The magnitude of the control pulse is then lowered to an intermediate voltage when the latch is set. Current will then flow through the isolation transistor into the low voltage side of the latch, discharging the line connected to the low voltage side. The isolation transistor on the high voltage side of the latch will remain off. The circuit illustrated in Fig. 1 provides the same result without the need for a control pulse. In the operation of the circuit of Fig. 1, nodes A and B and bit/ sense lines BS1 and BS2 are restored to the high voltage VH through P channel transistors T1, T2, T3 and T4 by lowering the voltage of terminals R connected to the control electrodes of these transistors. After a signal is developed on the bit/sense lines BS1 and BS2, the voltage on the node SL is lowered. Assuming a larger or more positive signal is established on BS2, N channel transistor T9 will cond...