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Self-Aligned Epitaxial Base Transistor

IP.com Disclosure Number: IPCOM000047576D
Original Publication Date: 1983-Dec-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 53K

Publishing Venue

IBM

Related People

Riseman, J: AUTHOR

Abstract

It is known to use a polysilicon extrinsic base in bipolar integrated circuits. The polysilicon used in the structure is deposited by chemical vapor deposition techniques. The present process uses the following epitaxial deposition method to provide an analogous structure. The process begins with an isolated monocrystalline silicon structure containing a subcollector region 8, a collector reach-through region 12 isolated from the base-emitter region 14 by isolation 16. Isolation region 18 isolates the bipolar device from similar such devices. Epitaxially grow silicon with, first, a high temperature surface cleaning step at about 1150ŒC, and then at a lower temperature of about 1050ŒC deposit silicon to a thickness of about 300 to 500 nanometers.

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Self-Aligned Epitaxial Base Transistor

It is known to use a polysilicon extrinsic base in bipolar integrated circuits. The polysilicon used in the structure is deposited by chemical vapor deposition techniques. The present process uses the following epitaxial deposition method to provide an analogous structure. The process begins with an isolated monocrystalline silicon structure containing a subcollector region 8, a collector reach-through region 12 isolated from the base-emitter region 14 by isolation 16. Isolation region 18 isolates the bipolar device from similar such devices. Epitaxially grow silicon with, first, a high temperature surface cleaning step at about 1150OEC, and then at a lower temperature of about 1050OEC deposit silicon to a thickness of about 300 to 500 nanometers. Single crystal silicon 20 forms on the single crystal areas, and polysilicon 22 over silicon dioxide. The layers 20, 22 are boron doped by ion implantation to a depth of about 100 nanometers with a dose of 1015/cm2 to produce the Fig. 1 structure. Deposit or grow silicon dioxide layer 24 on silicon layers 20, 22, as shown in Fig. 2. Openings are made through the silicon dioxide and epitaxial silicon layers for the intrinsic base and emitter regions by conventional techniques. The intrinsic base region 26 is formed as usual. Sidewall isolation 28 is shown formed upon the vertical edges of the opening. Then, the emitter region 30 is formed. The extrinsic base region 32 is formed by o...