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Improved Writing Scheme for a CTS Memory Cell

IP.com Disclosure Number: IPCOM000047589D
Original Publication Date: 1983-Dec-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 43K

Publishing Venue

IBM

Related People

Daghir, KS: AUTHOR [+2]

Abstract

In the present writing scheme for a Complementary Transistor Switch (CTS) memory cell [*] as shown in Fig. 1, node A is pulled down and node B is raised. Immediately VH is applied to BR1 through T2 while T1 is still cut off. Assume node R voltage is lower than that of node L initially. In order to flip the nodes L and R inside the cell, BR1 has to be raised to a higher voltage so that node R voltage is allowed to be higher than node L voltage, and the cell is written into a new state. It is clear from Fig. 1 that node BR1 voltage level is higher than that of node VA during writing and a current will be flowing from node BR1 to VA. As the current source T3 is usually small and not enough to absorb the "spilled over" current from BR1 to VA, this would cause VA voltage to rise above the previous level.

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Improved Writing Scheme for a CTS Memory Cell

In the present writing scheme for a Complementary Transistor Switch (CTS) memory cell [*] as shown in Fig. 1, node A is pulled down and node B is raised. Immediately VH is applied to BR1 through T2 while T1 is still cut off. Assume node R voltage is lower than that of node L initially. In order to flip the nodes L and R inside the cell, BR1 has to be raised to a higher voltage so that node R voltage is allowed to be higher than node L voltage, and the cell is written into a new state. It is clear from Fig. 1 that node BR1 voltage level is higher than that of node VA during writing and a current will be flowing from node BR1 to VA. As the current source T3 is usually small and not enough to absorb the "spilled over" current from BR1 to VA, this would cause VA voltage to rise above the previous level. Because of this, part of the "spilled over" current is now flowing from VA to BL1 through RX1. This current will go through D1 and raise node L level. This would not only delay the flipping of the cell to a new state, but under certain environmental conditions would prevent the cell from being written at all. An improved writing scheme is proposed as shown in Fig. 2. It is noted that R/W is an input Read and Write Control line. The system is in "write" mode when the R/W line is at a down level. When the R/W line is down, TX is cut off, R1 and TX1 form a current mirror to turn TX2 on whose collector is now connected to VA....