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High Performance/Density Dynamic RAM Cell

IP.com Disclosure Number: IPCOM000047592D
Original Publication Date: 1983-Dec-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 58K

Publishing Venue

IBM

Related People

Carballo, RA: AUTHOR [+3]

Abstract

A dynamic random-access memory (RAM) cell is shown in Fig. 1 which offers several advantages. The first advantage is high density since it requires no large storage area as does the conventional one-transistor cell, no column sense amplifier is required due to large signal, and its readout is non-destructive. Also, no dummy cell is needed for sensing. Another advantage is a large sense signal, since each cell has built-in amplification which obviates the need for column sense amplifiers. Access time is also shorter due to the fast sensing. The third advantage is high a-particle immunity because built-in potential exists between the storage node and the substrate. It rejects extraneous carriers from the substrate. Further, the RAM cell structure is CMOS compatible.

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High Performance/Density Dynamic RAM Cell

A dynamic random-access memory (RAM) cell is shown in Fig. 1 which offers several advantages. The first advantage is high density since it requires no large storage area as does the conventional one-transistor cell, no column sense amplifier is required due to large signal, and its readout is non-destructive. Also, no dummy cell is needed for sensing. Another advantage is a large sense signal, since each cell has built-in amplification which obviates the need for column sense amplifiers. Access time is also shorter due to the fast sensing. The third advantage is high a-particle immunity because built-in potential exists between the storage node and the substrate. It rejects extraneous carriers from the substrate. Further, the RAM cell structure is CMOS compatible. This RAM cell requires P-well on which CMOS devices can be built for peripheral circuits. Lastly, there is technological simplicity, since no buried layer or epitaxial layer is required. All processing steps are compatible with existing double-polysilicon gate technology. Fig. 1 shows the cross-section of the RAM cell structure which is isolated by recessed oxide isolation (ROX) from other such structures. Fig. 2 illustrates its equivalent circuit. The cell consists of 3 devices merged in a unique way. They are formed within a region of monocrystalline silicon surrounded by ROX. The metal oxide semiconductor field-effect transistor (MOSFET) device is responsible...